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**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**HT12/+/A      Single 286 AT Chip with EMS support            c:Aug90
***Info:
The  HT12, an IBM  PC/AT compatible  chip, supports  the 80286  CPU at
clock speeds  to 16MHz.  This  highly integrated chip  solution offers
high  performance  and  reliability,  with  low  cost,  minimal  power
consumption,  and low  board-space requirements.  It differs  from the
HT11 by the addition of 4 EMS Registers and an EMS Software Driver.

A  fully PC/AT  compatible system  is  implemented with  this chip  by
adding a CPU/NPU, KBD CNTRL, RTC,  BIOS, Memory and a few low cost TTL
devices.

This  chip supports  64K, 256K  and 1M,  x1 and  x4, DRAMs  in config-
urations up  to 4 Meg.   A 12.5MHz 0  wait-state system can  be imple-
mented using  80ns DRAMs  while a 10MHz  0 wait-state  system requires
100ns  DRAMs.  The  memory  controller also  supports  the shadow  RAM
feature and the  Split Memory option.  The Split  Memory option allows
the System RAM located between 640K and 1M to be remapped above top of
memory.

The HT12 contains CPU  and peripheral support functions; including DMA
controllers, a  memory mapper, timer/counters,  interrupt controllers,
and a bus controller.  This  chip replaces board address buffers, data
transceivers,  memory  drivers, parity  generators  and their  support
circuits. This chip is packaged in a 160 pin Flat Pack.

***Configurations:...
***Features:...
**HT18          80386SX Single Chip                            c:Sep91...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92
***Info:...
***Configurations:...
***Features:
o   25MHz operation at 2.7V to 3.6V
o   Extensive power management features
o   SMI support
o   Local Bus Interface
o   CPU clock control
o   16 general purpose I/O pins
o   2 programmable chip selects
o   44 event activity monitor
o   ISA bus refresh control
o   Up to 4 banks of 512Kb, 1 Mb and 4Mb DRAM
o   Flexible DRAM controller
o   Slow and Self refresh DRAM modes
o   Page mode DRAM accesses
o   DRAM page interleaving
o   4 register EMS
o   BIOS shadowing
o   Relocation for unused DRAM segments
o   PROM Write Enable for FLASH support
o   208 pin PQFP

**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
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