[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:
Date source: 1995_Intel_Pentium_Processors_and_Related_Components.pdf

Information taken from: 
            1995_Intel_Pentium_Processors_and_Related_Components.pdf*
                                         8249x Cache controllers.pdf**
>*  Datasheet dated Nov'94
>** Datasheet undated, whole document dated '95

The info and features section have  been solely sourced from the first
source.   The  second source  provides  far  more detail.   Additional
information in the configurations section  and below have been sourced
from the second.

"Although the 82497 Cache Controller  is part of the Pentium processor
(735\90, 815\100, 1000\120, 1110\133) CPU-Cache Chip Set and the 82496
Cache  Controller is part  of the  Pentium Processor  (510\60, 567\66)
Chip  Set, the  two parts  are functionally  identical except  for the
differences noted in this section." - p491

Aside  from some  minor  differences in  pin  configuration, the  main
difference is the direct support  for 3.3V processors. This chipset is
still a 5V part. The cache operates at bus speed, max 66MHz.


This  chip was  used on  the Pentium  90MHz CPU  complexes of  Intel's
Xpress  platform.   Specifically  the BXCPUPENT90  (Single  90MHz,  16
82492s). Also found on IBM 9595/Server 500 Pentium 90MHz complexes.

***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT12/+/A      Single 286 AT Chip with EMS support            c:Aug90
***Info:...
***Configurations:...
***Features:...
**HT18          80386SX Single Chip                            c:Sep91...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92
***Info:
The HT25  is the industry’s first  3-Volt single chip  core logic with
integrated  power management  for  386SX based  3-Volt systems.   Pro-
grammable  power  management features  give  system manufacturers  the
flexibility of offering customized system solutions.

GENERAL DESCRIPTION
The HT25 is a  PC/AT1M compatible single-chip solution with integrated
power management  designed to operate in a  3-Volt system environment.
This highly integrated chip facilitates  the design of low power, high
performance portable systems.  The  HT25 supports 3-Volt 386SX CPUs at
clock  speeds  up  to  25MHz  at  2.7V to  3.6V.   It  supports  power
management functions using the System Management Mode (SMM).

Flexible  power  management is  the  cornerstone  of the  HT25.   This
approach provides  power saving  features that  can be  customized for
product  differentiation.  Power  management  features include  system
activity monitors  and general purpose  I/O pins.  The  HT25 generates
System Management  Interrupt (SMI) to process  activity information or
when access  to powered down  peripherals is detected.   Further power
savings are achieved through the HT25’s ability to control CPU and NPU
clocks and support for slow refresh and self refresh DRAMs.

The HT25 Memory Controller features BIOS Shadowing, Memory Relocation,
EMS, Page  Mode Memory Access and Interleaving.  The memory controller
allows memory banks to be reordered to allow more efficient memory in-
terleaving. The HT25 supports 512Kb, le, and 4Mb DRAMs.

The HT25 architecture  is optimized for 3-Volt system  designs, the SD
bus acknowledge input provides a flexible I/O bus architecture and the
XD bus is buffered directly  from the HT25.  Further, no external data
bus buffers are required for a closed 3V system.

***Configurations:...
***Features:...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...