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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82498 Cache Controller and multiple 82493 Cache SRAMs combine with
the Pentium processor (735/90,  815/100) and future Pentium Processors
to form a CPU Cache chip set designed for high performance servers and
function-rich  desktops. The high-speed  interconnect between  the CPU
and  cache components has  been optimized  to provide  zero-wait state
operation. This CPU  Cache chip set is fully  compatible with existing
software,  and has new  data integrity  features for  mission critical
applications.

The 82498 Cache Controller implements the MESI write-back protocol for
full multiprocessing support.  Dual ported buffers and registers allow
the 82498  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82493 is a customized high-performance SRAM that supports 64-, and
128-bit  wide memory  bus widths,  32-,  and 64-byte  line sizes,  and
optional sectoring. The  data path between the CPU  bus and memory bus
is  separated  by  the  82493,  allowing  the  CPU  bus  to  handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91
***Info:...
***Configurations:...
***Features:
o   Single Chip 80386SX/286 PC/AT Compatible Solution for CPU Clock 
    Speeds to 20MHz
o   SX Mode or 286 Mode
o   Supports up to 8 MB DRAM using 1M or 256K Devices in by 1 or 4 
    configuration
o   Page Mode and 2 or 4-Way Interleaving
o   LIM EMS 4.0 Support in Hardware using 2 Sets of 32 EMS Registers
o   8-Bit or 16-Bit BIOS Support
o   Asynchronous AT Bus Clock
o   Supports up to 12 MHz Backplane Operation
o   Programmable DRAM Timing
o   Port 92 Alternate GATEA20 and Hot Reset
o   Shadow RAM support over entire C0000-DFFFF range in 16K 
    increments
o   BIOS Shadow support in 64K increments
o   Built-in Sleep Mode
o   Three-state control pins for board level testing
o   HCMOS Technology

**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
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*UMC...
*Unresearched:...
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*ZyMOS...
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