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**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
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**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**HT12/+/A      Single 286 AT Chip with EMS support            c:Aug90
***Info:
The  HT12, an IBM  PC/AT compatible  chip, supports  the 80286  CPU at
clock speeds  to 16MHz.  This  highly integrated chip  solution offers
high  performance  and  reliability,  with  low  cost,  minimal  power
consumption,  and low  board-space requirements.  It differs  from the
HT11 by the addition of 4 EMS Registers and an EMS Software Driver.

A  fully PC/AT  compatible system  is  implemented with  this chip  by
adding a CPU/NPU, KBD CNTRL, RTC,  BIOS, Memory and a few low cost TTL
devices.

This  chip supports  64K, 256K  and 1M,  x1 and  x4, DRAMs  in config-
urations up  to 4 Meg.   A 12.5MHz 0  wait-state system can  be imple-
mented using  80ns DRAMs  while a 10MHz  0 wait-state  system requires
100ns  DRAMs.  The  memory  controller also  supports  the shadow  RAM
feature and the  Split Memory option.  The Split  Memory option allows
the System RAM located between 640K and 1M to be remapped above top of
memory.

The HT12 contains CPU  and peripheral support functions; including DMA
controllers, a  memory mapper, timer/counters,  interrupt controllers,
and a bus controller.  This  chip replaces board address buffers, data
transceivers,  memory  drivers, parity  generators  and their  support
circuits. This chip is packaged in a 160 pin Flat Pack.

***Configurations:...
***Features:...
**HT18          80386SX Single Chip                            c:Sep91
***Info:
The HT18  is an advanced PC/AT compatible,  single-chip 80386SX design
solution. This  highly integrated single chip allows  simple, low cost
system  design options  while  featuring high  performance, low  power
consumption,  and minimum board  space requirements.   Advanced memory
management features  include support  for page mode,  with 2  or 4-way
interleaving  in both pipelined  and non-pipelined  modes(18A/B only).
Extended Hardware EMS  options include dual sets of  32 registers with
multiple context operation. Revisions A/B support 256K and 1M DRAMs in
1 by 1,  1 by 4, and 1  by 9 device configurations. Rev  C supports 4M
devices, as well.  A Shadow RAM  option for System Video BIOS and dual
or single system ROM BIOS support adds to overall design versatility.

A  complete PC/AT  compatible  system with  advanced  features may  be
implemented with minimal external support logic. The HT18 performs all
CPU  and peripheral support  functions in  a single  chip.  Integrated
device  functions include  DMA Controllers,  a Memory  Mapper, Timers,
Counters, Interrupt  Controllers, a Bus Controller  and all supporting
circuitry for PC core logic requirements. An asynchronous AT Bus clock
allows  for a  constant 8MHz  Bus clock  rate for  highest  bus device
compatibility as defined in IEEE Spec P996. This device is packaged in
a 208-pin  Plastic Quad Flat  Pack combining several  external buffers
into this space saving solution.

***Configurations:...
***Features:...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
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