[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:
The Intel 82495XP cache controller and 82490XP cache RAM, when coupled
with a user-implemented memory  bus controller, provide a second-level
cache  subsystem  that eliminates  the  memory  latency and  bandwidth
bottleneck for  a wide  range of multiprocessor  systems based  on the
i860 XP  microprocessor. The CPU  interface is optimized to  serve the
i860  XP microprocessor  with zero  wait  states at  up to  50 MHz.  A
secondary cache  built from the  82495XP and 82490XP isolates  the CPU
from  the memory subsystem;  the memory  can run  slower and  follow a
different protocol than the i860 XP microprocessor.
         
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT18          80386SX Single Chip                            c:Sep91
***Info:
The HT18  is an advanced PC/AT compatible,  single-chip 80386SX design
solution. This  highly integrated single chip allows  simple, low cost
system  design options  while  featuring high  performance, low  power
consumption,  and minimum board  space requirements.   Advanced memory
management features  include support  for page mode,  with 2  or 4-way
interleaving  in both pipelined  and non-pipelined  modes(18A/B only).
Extended Hardware EMS  options include dual sets of  32 registers with
multiple context operation. Revisions A/B support 256K and 1M DRAMs in
1 by 1,  1 by 4, and 1  by 9 device configurations. Rev  C supports 4M
devices, as well.  A Shadow RAM  option for System Video BIOS and dual
or single system ROM BIOS support adds to overall design versatility.

A  complete PC/AT  compatible  system with  advanced  features may  be
implemented with minimal external support logic. The HT18 performs all
CPU  and peripheral support  functions in  a single  chip.  Integrated
device  functions include  DMA Controllers,  a Memory  Mapper, Timers,
Counters, Interrupt  Controllers, a Bus Controller  and all supporting
circuitry for PC core logic requirements. An asynchronous AT Bus clock
allows  for a  constant 8MHz  Bus clock  rate for  highest  bus device
compatibility as defined in IEEE Spec P996. This device is packaged in
a 208-pin  Plastic Quad Flat  Pack combining several  external buffers
into this space saving solution.

***Configurations:...
***Features:...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...