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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
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**HT18          80386SX Single Chip                            c:Sep91
***Info:
The HT18  is an advanced PC/AT compatible,  single-chip 80386SX design
solution. This  highly integrated single chip allows  simple, low cost
system  design options  while  featuring high  performance, low  power
consumption,  and minimum board  space requirements.   Advanced memory
management features  include support  for page mode,  with 2  or 4-way
interleaving  in both pipelined  and non-pipelined  modes(18A/B only).
Extended Hardware EMS  options include dual sets of  32 registers with
multiple context operation. Revisions A/B support 256K and 1M DRAMs in
1 by 1,  1 by 4, and 1  by 9 device configurations. Rev  C supports 4M
devices, as well.  A Shadow RAM  option for System Video BIOS and dual
or single system ROM BIOS support adds to overall design versatility.

A  complete PC/AT  compatible  system with  advanced  features may  be
implemented with minimal external support logic. The HT18 performs all
CPU  and peripheral support  functions in  a single  chip.  Integrated
device  functions include  DMA Controllers,  a Memory  Mapper, Timers,
Counters, Interrupt  Controllers, a Bus Controller  and all supporting
circuitry for PC core logic requirements. An asynchronous AT Bus clock
allows  for a  constant 8MHz  Bus clock  rate for  highest  bus device
compatibility as defined in IEEE Spec P996. This device is packaged in
a 208-pin  Plastic Quad Flat  Pack combining several  external buffers
into this space saving solution.

***Configurations:...
***Features:
o   Highly Integrated, Single Chip 80386SX AT Compatible Solution
o   Special Multiple Context Hardware EMS Support (LIM 4.0 compatible) 
    using 2 sets of 32 EMS Registers
o   Single or Dual BIOS
o   Shadow RAM support over entire C0000 to DFFFF Address range in 16K 
    increments, E0000 to FFFFF in 64K increments
o   Page Mode and 2-way Interleaving
o   Supports up to 12MHz AT Bus Clock
o   High Performance Muxed DRAM Interleave
o   Programmable DRAM timing
o   Asynchronous AT Bus Clock
o   Three-State Test Mode
o   16-Bit ROM BIOS Support

HT 18A/B Special Features
o   16 and 20 MHz CPU Clock Speeds
o   Supports up to 8M CPU Memory using combinations of 64K, 256K and 
    1M Devices
o   4 Bank, 4-way Interleave Mode

HT18C/25MHz Special Features
o   16, 20 and 25MHz CPU Clock Speeds
o   Supports up to 20M with EMS CPU Memory using combinations of 256K, 
    1M and 4M Devices

**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
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