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**M1489/87       FinALi-486 PCI Chipset                         <Feb95
***Info:
ALi's M1489/M1487 PCI chipset is  the most cost effective PCI solution
available. M1489/M1487  enables top-to-bottom PCI in  486 CPU systems,
offering superior price/performance for mainstream PCI-ISA systems.

M1489/M1487 highly  integrates the DRAM controller,  L2 cache control-
ler,  Host,  PCI, and  ISA  interface, as  well  as  the standard  ISA
functions:  DMA controller,  interrupt controller,  timer/counter, RTC
(Real Time Clock),  and keyboard controller. Additionally, M1489/M1487
incorporates the high performance Local  Bus IDE allowing a system de-
signer to implement Local bus IDE with no additional cost. M1489/M1487
is a  highly integrated  solution requiring minimized  TTL components,
enabling PCI-ISA designs at costs equal to or lower than comparable VL
Bus designs.

M1489 (Cache Memory PCI Controller:  CMP) integrates the L2 cache con-
troller  and  the  DRAM  controller.  The  cache  controller  supports
write-back cache  policies and cache size  from 128K to 1M  byte in an
interleaved  or non-interleaved  configuration.   The DRAM  controller
interfaces DRAM  to the Host  bus, PCI bus,  and Link bus.   M1489 can
support   EDO  3/5V   DRAM,   standard  DRAM,   and  flexible   timing
select. M1489  also integrates  intelligent Host to  PCI, PCI  to Host
buffer  to achieve high  performance.  Also,  M1489 provides  the high
performance Local Bus IDE interface.

M1487 (ISA Bridge Controller: IBC) provides the bridge between the ISA
bus, PCI  bus, and Host bus.  IBC integrates the  common I/O functions
found in  today's ISA  based systems: a  seven channel DMA,  two 82C59
interrupt controllers,  8254 timer/ counter, deep  green function, and
control logic for NMI generation. IBC also has built-in 128 bytes RTC,
MC14069, KBC,  and 7406.   IBC also provides  the decode  for external
BIOS.

***Configurations:...
***Features:...
**M????          Genie, Quad Pentium  [no datasheet, some info]    c95...
**M1451/49       Aladdin    (Pentium) [no datasheet]                 ?...
**M1511/12/13    Aladdin II (Pentium) [no datasheet, some info] >Apr95...
**M1521/23       Aladdin III       50-66MHz                     <Nov96...
**M1531/33/43    Aladdin IV & IV+  50-83.3MHz                <05/28/97...
**M1541/42/33/43 Aladdin V & V+    50-100MHz                         ?...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99...
**M6117          386SX Single Chip PC                              <97...
**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT18          80386SX Single Chip                            c:Sep91
***Info:...
***Configurations:...
***Features:
o   Highly Integrated, Single Chip 80386SX AT Compatible Solution
o   Special Multiple Context Hardware EMS Support (LIM 4.0 compatible) 
    using 2 sets of 32 EMS Registers
o   Single or Dual BIOS
o   Shadow RAM support over entire C0000 to DFFFF Address range in 16K 
    increments, E0000 to FFFFF in 64K increments
o   Page Mode and 2-way Interleaving
o   Supports up to 12MHz AT Bus Clock
o   High Performance Muxed DRAM Interleave
o   Programmable DRAM timing
o   Asynchronous AT Bus Clock
o   Three-State Test Mode
o   16-Bit ROM BIOS Support

HT 18A/B Special Features
o   16 and 20 MHz CPU Clock Speeds
o   Supports up to 8M CPU Memory using combinations of 64K, 256K and 
    1M Devices
o   4 Bank, 4-way Interleave Mode

HT18C/25MHz Special Features
o   16, 20 and 25MHz CPU Clock Speeds
o   Supports up to 20M with EMS CPU Memory using combinations of 256K, 
    1M and 4M Devices

**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...