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**M1489/87 FinALi-486 PCI Chipset <Feb95
***Info:...
***Configurations:...
***Features:
Supported CPUs
o Supports AMD 486D4 and X5, Intel 486, P24T, P24D, DX4, SL-
Enhanced, Cyrix M7, UMC U5 and AMD AM486DXL CPUs in 25, 33, 40,
50, 66, 100 and 133 MHz 3V/5V CPU interface
o Supports CPU L1 writeback
o Supports Cyrix's linear addressing
L2 Cache Controller
o Write Back cache with standard SRAM
o 8 Tag Bit, always force Dirty or 7 Tag Bit, 1 Dirty bit
o Supports cache size of 128K to 1M with 32KX8, 64Kx8, 128Kx8
o Supports 2-1-1-1 read burst timing
o Write hit 0 wait support
DRAM Controller
o Supports 5V/3V EDO DRAM
o Flexible DRAM type & Timing support
o Supports up to 128M bytes, 4-bank DRAM size
o Supports hidden refresh and RAS only normal refresh
Built in RTC & KBC
o Built in 128 byte Real Time Clock (RTC) & MC14069
o Built in Keyboard Controller (KBC) & 7406
Built in IDE Controller
o Dedicated IDE pins, concurrent with PCI bus
o 4x32 bits Read-Ahead buffer and Write-Post buffer support
o Supports through ATA PIO mode 3, 4 harddisk
PCI Local Bus
o Synchronous 20, 25, 33 MHz PCI clock
o Supports PCI rev 2.0 with 4 PCI devices, 3 slot PCI masters, 1
slot PCI slave
o Supports 4 PCI interrupt steering input
o Supports CPU to PCI 4 layer DWord write buffer
o Supports PCI to memory 8 layer DWord write buffer
o Supports PCI parity
Power Management
o Deep Green SMM, SMI
o Suspend switch support, Green mode state is LED indicated
o CLKCTR for clock generator control
Process/Packing
o M1489 0.6u, 208-pin PQFP
o M1487 0.6u, 160-pin PQFP
**M???? Genie, Quad Pentium [no datasheet, some info] c95...
**M1451/49 Aladdin (Pentium) [no datasheet] ?...
**M1511/12/13 Aladdin II (Pentium) [no datasheet, some info] >Apr95...
**M1521/23 Aladdin III 50-66MHz <Nov96...
**M1531/33/43 Aladdin IV & IV+ 50-83.3MHz <05/28/97...
**M1541/42/33/43 Aladdin V & V+ 50-100MHz ?...
**M1561/43/35D Aladdin 7 ArtX [no datasheet, some info] 11/08/99...
**M6117 386SX Single Chip PC <97...
**
**Support Chips:
**M1535/D South Bridge ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HT18 80386SX Single Chip c:Sep91
***Info:
The HT18 is an advanced PC/AT compatible, single-chip 80386SX design
solution. This highly integrated single chip allows simple, low cost
system design options while featuring high performance, low power
consumption, and minimum board space requirements. Advanced memory
management features include support for page mode, with 2 or 4-way
interleaving in both pipelined and non-pipelined modes(18A/B only).
Extended Hardware EMS options include dual sets of 32 registers with
multiple context operation. Revisions A/B support 256K and 1M DRAMs in
1 by 1, 1 by 4, and 1 by 9 device configurations. Rev C supports 4M
devices, as well. A Shadow RAM option for System Video BIOS and dual
or single system ROM BIOS support adds to overall design versatility.
A complete PC/AT compatible system with advanced features may be
implemented with minimal external support logic. The HT18 performs all
CPU and peripheral support functions in a single chip. Integrated
device functions include DMA Controllers, a Memory Mapper, Timers,
Counters, Interrupt Controllers, a Bus Controller and all supporting
circuitry for PC core logic requirements. An asynchronous AT Bus clock
allows for a constant 8MHz Bus clock rate for highest bus device
compatibility as defined in IEEE Spec P996. This device is packaged in
a 208-pin Plastic Quad Flat Pack combining several external buffers
into this space saving solution.
***Configurations:...
***Features:...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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