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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:
o   Two-Way, Set Associative, Secondary Cache for i860 XP 
    Microprocessor
o   50 MHz "No Glue" Interface with CPU
o   Configurable
    - Cache Size 256 or 512 Kbytes
    - Line Width 32, 64 or 128 Bytes
    - Memory Bus Width 64 or 128 Bits
o   Dual-Ported Structure Permits Simultaneous Operations on CPU and
    Memory Buses
o   Efficient MRU Way Prediction
    - Zero Wait States on MRU Hit
    - One Walt State on MRU Miss
o   Dynamically Selectable Update Policies
    - Write-Through
    - Write-Once
    - Write-Back
o   MESI Cache Consistency Protocol
o   Hardware Cache Snooping
o   Maintains Consistency with Primary Cache via Inclusion Principle
o   Flexible User-Implemented Memory Interface Enables Wide Range of
    Product Differentiation
    - Clocked or Strobed
    - Synchronous or Asynchronous
    - Plpelining
    - Memory Bus Protocol
o   82495XP Cache Controller Available in 208-Lead Ceramic Pin Grid 
    Array Package
o   82490XP Cache RAM Available in 84-Lead Plastic Quad Flatpack 
    Package

**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT44          Secondary Cache                                c:Jun92
***Info:
The  HT44 is  a  look-aside write-through,  80486SX,  486DX or  486DX2
secondary cache  controller. It is  packaged in an  inexpensive 84-pin
plastic-leaded chip carrier (PLCC).

Architecture
With  its look-aside architecture,  the HT44  fits beside  the CPU-to-
Memory bus  and not in  the data path.   Therefore, once the  HT44 has
been designed  into a  486 system, it  can be populated  for secondary
cache systems or left vacant for non-secondary cache systems. The HT44
is direct-mapped to the available address space.

Performance
The  HT44  has a  number  of  performance  enhancing features.   These
include zero-waitstate burst line fills  to the 486 on secondary cache
hits, and simultaneous 486 and secondary cache updates on read misses.

Memory Configurations
The HT44 supports  cache sizes from 32KBytes to  1MB. Both synchronous
and asynchronous  SRAMs are supported.  25ns SRAMs are  sufficient for
zero-wait-state operation at 33MHz.

Chip Set Support
The HT44 can,  be implemented with minimal glue logic  in a 486 system
with the  HTK340 (code  name Shasta) chip  set.  The registers  in the
HTK340  allow  for programming  of  non-cacheable and  write-protected
areas of  memory. The  HTK340 will support  the HT44  with synchronous
SRAMs only.   Future Headland chip sets will  support both synchronous
and asynchronous SRAM designs.

The HT44  can also be used  with some third-party  chip sets, however,
additional glue logic may be required.

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