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**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:
o   50 MHz Intel486 DX CPU 
    - RISC Integer Core with Frequent Instructions Executing in One 
      Clock
    - 160 Mbyte/Sec Burst Bus
    - 41 Dhrystone MIPs
    - 11.5M Double Precision Whetstones/Sec.
    - On-Chip Cache and FPU
o   Highly Flexible
    - Supports 128 Kbyte and 256 Kbyte Configurations
    - Complete MESI Protocol Support
    - 32- or 64-Bit Memory Bus Width
    - Synchronous, Asynchronous, and Strobed Memory Bus Protocols
    - Variable Cache Line Sizes and Sectoring
    - Cache Data Parity Option
o   High Performance Second Level Cache
    - Two-Way Set Associative
    - Write-Back or Write Through Cache
    - Zero Wait State Cache Access
    - Concurrent CPU Bus, Memory Bus, and Internal Array Operation
o   Full Multiprocessing Support
    - Implements MESI Write-Back Cache Protocol
    - Low Bus Utilization
    - Automatically Maintains 1st Level Cache Consistency
    - Supports Read-for-Ownership, Write-Allocation, and Cache-to-
      Cache Transfers

**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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*OPTi...
**82C802G/GP     System/Power Management Controller (cached)      c:93
***Notes:...
***Info:
The  82C802G/GP  provides  a  highly  integrated  solution  for  fully
compatible,  high  performance  PC/AT  platforms.  This  chipset  will
support  486SX/DX/DX2/DX4 and  P24T microprocessors  in the  most cost
effective  and power  efficient  designs available  today.  For  power
users this  chipset offers optimum performance for  systems running up
to 50MHz.

Based  fundamentally  on  OPTi’s   proven  82C801  and  82C802  design
architectures,  the 82C802G/GP  adds additional  memory configurations
and  extensive power management  control for  the processor  and other
motherboard components.

The  82C802G/GP supports  the latest  in write-back  processor designs
from Intel, AMD, and Cyrix, as  well as supporting the AT bus and VESA
local  bus for  compatibility and  performance.  It  also  includes an
82C206  Integrated  Peripherals  Controller  (IPC), all  in  a  single
208-pin PQFP (Plastic Quad Plat Pack) package for low cost.

Power Management Block
Figure  2-1  [see  datasheet]   exemplifies  the  flexibility  of  the
82C802G/GP/82C602   GREEN   strategy.   System  designs   can   easily
accommodate  both SLe and  non-SLe CPUs.  If an  Intel non-SLe  CPU is
used. SMI#, SMIACT#, and FLUSH# are no connects. One design can easily
accommodate  both  types  of   processors  with  minimal  changes  for
upgrades.

***Configurations:...
***Features:...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
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