[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395DX High Performance Smart Cache 06/18/90
***Notes:...
***Info:
The 82395DX High Performance 82395DX Smart Cache is a low cost, high
integration, 32-Bit peripheral for Intel's i386 DX Microprocessor. It
stores a copy of frequently accessed code or data from main memory to
on chip data RAM that can be accessed in zero wait states. The 82395DX
enables the 386 DX Microprocessor to run at near its full potential by
reducing the average number of wait states seen by the CPU to nearly
zero. The dual bus architecture allows another bus master to access
the System Bus while the 386 DX Microprocessor can operate out of the
82395DX's cache on the Local Bus. The 82395DX has a snooping
mechanism which maintains cache coherency during these cycles.
The 8239SDX is completely software transparent, protecting the
integrity of system software. High performance, low cost and board
space saving are achieved due to the high integration and new write
buffer architecture.
1.0 82395DX FUNCTIONAL OVERVIEW
1.1 Introduction
The primary function of a cache is to provide local storage for
frequently accessed memory locations. The cache intercepts memory
references and handles them directly without transferring the request
to the System Bus. This results in lower traffic on the System Bus and
decreases latency on the local bus. This leads to improved
performance for a processor on the Local Bus. By providing fast access
to frequently used code and data, the cache is able to reduce the
average memory access time of the 386 DX Microprocessor based system.
The 82395DX is a single chip cache subsystem specifically designed for
use with the 386 DX Microprocessor. The 82395DX integrates 16KB
cache, the Cache Directory and the Cache Control Logic onto one chip.
The 82395DX is expandable such that larger cache sizes are supported
by cascading 82395DXs. In a single 82395DX system, the 82395DX can map
4 Giga bytes of main memory into a 16KB cache. In the maximum con-
figuration of a four 82395DX system, the 4 Giga bytes of main memory
are mapped into a 64KB cache. The cache is unified for code and data
and is transparent to application software. The 82395DX provides a
cache consistency mechanism which guarantees that the cache has the
most recently updated version of the main memory. Consistency support
has no performance impact on the 386 DX Microprocessor. Section 1.2
covers all the 82395DX features.
The 8239SDX cache architecture is similar to the i486 Microprocessor’s
on-chip cache. The cache is four Way set associative with Pseudo LRU
replacement algorithm. The line size is 16B and a full line is
retrieved from the memory every cache miss. A TAG is associated with
every 16B line.
The 82395DX architecture allows for cache read hit cycles to run on
the Local Bus even when the System Bus is not available. 82395DX
incorporates a new write buffer cache architecture, which allows the
386 DX Microprocessor to continue operation without waiting for write
cycles to actually update the main memory.
A detailed description of the cache operation and parameters is
included in chapter 2.
The 82395DX has an interface to two electrically isolated busses. The
interface to the 386 DX Microprocessor bus is referred to as the Local
Bus (LB) interface. The interface to the main memory and other system
devices is referred to as the 82395DX System Bus (SB) interface. The
SB interface emulates the 386 DX Microprocessor. The SB interface, as
does the 386 DX Microprocessor, can be pipelined.
in addition, it is enhanced by an optional burst mode for Line
Fills. The burst mode provides faster line fills by allowing
consecutive read cycles to be executed at a rate of up to one DW per
clock cycle. Several bus masters (or several 82395DXs) can share the
same System Bus and the arbitration is done via the SHOLD/SHLDA/SBREQ
mechanism (similar to the i486 Microprocessor) along with
SFHOLD#. Using these arbitration mechanisms, the 82395DX is able to
support a multiprocessor system (multi 386 DX Microprocessor/82395DX
systems sharing the same memory).
Cache consistency is maintained by the SAHOLD/SEADS# snooping
mechanism, similar to the i486 microprocessor. The 82395DX is able to
run a zero wait state 386 DX Microprocessor non-pipelined read cycle
it the data exists in the cache. Memory write cycles can run with zero
wait states if the write buffer is not full.
The 82395DX cache organization provides a higher hit rate than other
standard configurations. The 82395DX, featuring the new high
performance write buffer cache architecture, provides full concurrency
between the electrically isolated Local Bus and System Bus. This
allows the 82395DX to service read hit cycles on the Local Bus while
running line fills or buffered write cycles on the System Bus.
Moreover, the user has the option to expand his cache system up to
64KB.
1.2 Features
1.2.1 82385-LIKE FEATURES
o The 82395DX maps the entire physical address range of the 386 DX
Microprocessor (4GB) into 16KB, 32KB, or 64KB cache (with one, two,
or four 82395DXs respectively).
o Unified code and data cache.
o Cache attributes are handled by hardware. Thus the 82395DX is
transparent to application software. This preserves the integrity of
system software and protects the users software investment.
o Double Word, Word and Byte writes, Double Word reads.
o Zero wait states in read hits and in buffered write cycles. All 386
DX Microprocessor cycles are non-pipelined. (Note: The 386 DX
Microprocessor must never be pipelined when used with the 82395DX -
NA# must be tied to Vcc).
o A hardware cache FLUSH# option. The 82395DX will invalidate all the
Tag Valid bits in the Cache Directory and clear the System Bus line
butter when FLUSH# is activated for a minimum of four CLK’s. The
line buffer is also FLUSH #ed.
o The 8239SDX supports non-cacheable accesses. The 82395DX internally
decodes the 387 DX Math Coprocessor accesses as Local Bus cycles.
o The system bus interface emulates a 386 DX Microprocessor interface.
o The 82395DX supports pipelined and non-pipelined system interface.
o Provides cache consistency (snooping): The 82395DX monitors the
System Bus address via SEADS# and invalidates the cache address if
the System Bus address matches a cached location.
1.2.2 NEW FEATURES
o 16KB on chip cache arranged in four banks, one bank for each way. In
Read hit cycles, one DW is read. In a write hit cycle, any byte
within the DW can be written. In cache fill cycle, the whole line
(16B) is written. This large line size increases the hit rate over
smaller line size caches.
o Cache architecture similar to the i486 Microprocessor cache: Four
Way SET associative with Pseudo LRU replacement algorithm. Line size
is 16B and a full line is retrieved from memory for every cache
miss. Tag. Tag Valid Bit and Write Protect Bit are associated with
every Line.
o New write buffer architecture with four DW deep write buffer
provides zero wait state memory write cycles. I/O, Halt/ Shutdown
and LOCK#ed writes are not buffered.
o Concurrent Line Buffer Cacheing: The 82395DX has a line buffer that
is used as additional memory. Before data gets written to the cache
memory at the completion of a Line Fill it is stored in this buffer.
Cache hit cycles to the line buffer can occur before the line is
written to the cache.
o Expandable: two 82395DXs support 32KB cache memory, four 82395DXs
support 64KB cache memory. This gives the user the option of config-
uring a system to meet their own performance requirements.
o In 387 DX Math Coprocessor accesses, the 82895DX drives the READYO#
in one wait state if the READYI# was not driven in the previous
clock.
Note that the timing of the 82395’5 READYO# generation for 387 DX
Math Coprocessor cycles is incompatible with 80287 timing.
o The 82395DX optionally decodes CPU accesses to Weitek 3167
Floating-Point Coprocessor address space (COOOOOOOH-ClFFFFFFH) as
Local Bus cycles. This option is enabled or disabled according to
the LBA# pin value at the falling edge of RESET.
o An enhanced System Bus interface:
a) Burst option is supported in line-fills similar to the i486
Microprocessor. SBRDY# (System Burst READY) is provided in
addition to SRDY#. A burst is always a 16 byte cache update which
is equivalent to four DW cycles. The i486 Microprocessor burst
order is supported.
b) System cacheability attribute is provided (SKEN#). SKEN# is used
to determine whether the current cycle is cacheable. If is used
to qualify Line Fill requests.
c) SHOLD/SHLDA/SBREQ system bus arbitration mechanism is supp-
orted. the same as in the i486 Microprocessor. A Multi 386
DX/82395DX cluster can share the same System Bus via this
mechanism.
d) SNENE# output (Next Near) is provided to simplify the interface
to DRAM controllers. DRAM page size of 2K is supported.
e) Fast HOLD function (SFHOLD#) is provided. This function allows
for multiprocessor support.
f) Cache invalidation cycles supported via SEADS#. This is the
mechanism used to provide cache coherency.
o Full Local Bus/System Bus concurrency is attained by:
a) Servicing cache read hit cycles on the Local Bus while completing
a Line Fill on the System Bus. The data requested by the 386 DX
Microprocessor was provided over the local bus as the first part
of the Line Fill.
b) Servicing cache read hit cycles on the Local Bus while executing
buffered write cycles on the system bus.
c) Servicing cache read hit cycles on the Local Bus while another
bus master is running (DMA, other 386 DX Microprocessor, 82395DX,
i486 Microprocessor, etc...) on the System Bus.
d) Buffering write cycles on the Local Bus while the system bus is
executing other cycles.
o Write protected areas are supported by the SWP# input. This enables
caching of ROM space or shadowed ROM space.
o No Post Input (NPI#) provided for disabling of write buffers per
cycle. This option supports memory mapped I/O designs.
o A20M# input provided for emulation of 8086 address wrap-around.
o SRAM test mode. in which the TAGRAM and the cache RAM are treated as
standard SRAM, is provided. A Tristate Output test mode is also pro-
vided for system debugging. in this mode the 82395DX is isolated
from the other devices in the board by floating all its outputs.
o Single chip, 196 lead PQFP package, 1 micron CHMOS-lV technology.
***Versions:...
***Features:...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03
Chips:
[82855GM](MCH) [82801DBM] (ICH4-M)
CPUs: Pentium M, Celeron M
DRAM Types: DDR 200/266/333
Mem Rows: --
DRAM Density: ?
Max Mem: 2GB
ECC/Parity: no
AGP speed: no?
Bus Speed: 400 MT/s (100 MHz QDR)
PCI Clock/Bus: 1/3 PCI 2.2
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved