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**82385SX     32-bit Cache Controller for 80386SX             01/25/89
***Notes:...
***Info:...
***Versions:...
***Features:
o   Improves 386 SX System Performance
    - Reduces Average CPU Wait States to Nearly Zero
    - Zero Wait State Read Hit
    - Zero Wait State Posted Memory Writes
    - Allows Other Masters to Access the System Bus More Readily
o   Hit Rates up to 99%
o   Optimized as 386 SX Companion
    - Simple 386 SX Interface
    - Part of Intel386-Based Compute Engine Including 387 SX Math 
      Coprocessor and 82370 Integrated System Peripheral
    - 16 MHz and 20 MHz Operation
o   Software Transparent
o   Synchronous Dual Bus Architecture
    - Bus Watching Maintains Cache Coherency
o   Maps Full 386 SX Address Space 
o   Flexible Cache Mapping Policies
    - Direct Mapped or 2-Way Set Associative Cache Organization
    - Supports Non-Cacheable Memory Space
    - Unified Cache for Code and Data
o   Integrates Cache Directory and Cache Management Logic
o   High Speed CHMOS Technology
    - 132-Pin PGA Package

**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90...
**82396SX     Smart Cache                                     12/17/90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**5120           Pentium PCI/ISA Chipset (Mobile)            <01/28/97
***Info:
The SiS5120  is a highly  integrated single chip solution  for Pentium
PCI/ISA system. It consists of Host-to-PCI bridge function, PCI to ISA
bridge  function,  PCI IDE  function,  Universal  Serial Bus  host/hub
function.

SiS 5120  supports Enhanced  Power Management, including  legacy Power
Management  Unit  and   Advanced  Configuration  and  Power  Interface
(ACPI).  It also  supports ATA  Synchronous DMA  transfer  protocol to
improve  the IDE performance  and Common  Architecture for  moving ISA
function to PCI to improve system performance.


***Versions:...
***Features:...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset                <04/02/95...
**5511/5512/5513 Pentium PCI/ISA                             <06/14/95...
**5571           (Trinity) Pentium PCI/ISA Chipset (75MHz)   <12/09/96...
**5581/5582      (Jessie)  Pentium PCI/ISA Chipset (75MHz)   <04/15/97...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
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