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**82385SX 32-bit Cache Controller for 80386SX 01/25/89
***Notes:...
***Info:
The 82385SX Cache Controller is a high performance peripheral for
Intel's 386 SX Microprocessor. It stores a copy of frequently accessed
code and data from main memory in a zero wait state local cache
memory. The 82385SX allows the 386 SX Microprocessor to run near its
full potential by reducing the average number of CPU wait states to
nearly zero. The dual bus architecture of the 82385SX allows other
masters to access system resources while the 386 SX CPU operates
locally out of its cache. In this situation, the 82385SX's "bus
watching" mechanism preserves cache coherency by monitoring the system
bus address lines at no cost to system or local throughput.
The 82385SX is completely software transparent, protecting the
integrity of system software. High performance and board space savings
are achieved because the 82385SX integrates a cache directory and all
cache management logic on one chip.
1.0 82385SX FUNCTIONAL OVERVIEW
The 82385SX Cache Controller is a high performance peripheral for
Intel's 386 SX microprocessor. This chapter provides an overview of
the 82385SX, and of the basic architecture and operation of a 386 SX
CPU/ 82385SX system.
1.1 82385 OVERVIEW
The main function of a cache memory system is to provide fast local
storage for frequently accessed code and data. The cache system
intercepts 386 SX memory references to see if the required data
resides in the cache. If the data resides in the cache (a hit), it is
returned to the 386 SX without incurring wait states. If the data is
not cached (a miss), the reference is forwarded to the system and the
data retrieved from main memory. An efficient cache will yield a high
"hit rate" (the ratio of cache hits to total 386 SX accesses), such
that the majority of accesses are serviced with zero wait states. The
net effect is that the wait states incurred in a relatively infrequent
miss are averaged over a large number of accesses, resulting in an
average of nearly zero wait states per access. Since cache hits are
serviced locally, a processor operating out of its local cache has a
much lower "bus utilization" which reduces system bus bandwidth
requirements, making more bandwidth available to other bus masters.
The 82385SX Cache Controller integrates a cache directory and all
cache management logic required to support an external 16 Kbyte
cache. The cache directory structure is such that the entire physical
address range of the 386 SX is mapped into the cache. Provision is
made to allow areas of memory to be set aside a non-cacheable. The
user has two cache organization options: direct mapped and 2-way set
associative. Both provide the high hit rates necessary to make a
large, relatively slow main memory array look like a fast, zero wait
state memory to the 386 SX.
A good hit rate is an essential ingredient of a successful cache
implementation. Hit rate is the measure, of how efficient a cache is
in maintaining a copy of the most frequently requested code and data.
However, efficiency is not the only factor for performance
consideration. Just as essential are sound cache management policies.
These policies refer to the handling of 386 SX writes, preservation of
cache coherency, and ease of system design. The 82385SX's "posted
write" capability allows the majority of 386 SX writes, including
non-cacheable, to run with zero wait states, and the 82385SX's "bus
watching" mechanism preserves cache coherency with no impact on system
performance. Physically, the 82385SX ties directly to the 386 SX with
virtually no external logiC.
***Versions:...
***Features:...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90
***Notes:...
***Info:...
***Versions:
82485 25MHz
82485 33MHz
****485Turbocache module...
***Features:...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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*OPTi...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92
***Info:...
***Configurations:...
***Features:...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
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