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*Intel...
**82385 32-bit Cache Controller for 80386 09/29/87
***Notes:...
***Info:
The 82385 Cache Controller is a high performance 32-bit peripheral for
Intel's 80386 Microprocessor. It stores a copy of frequently accessed
code and data from main memory in a zero wait state local cache
memory. The 82385 enables the 80386 to run at its full potential by
reducing the average number of CPU wait states to nearly zero. The
dual bus architecture of the 82385 allows other masters to access
system resources while the 80386 operates locally out of its cache.
In this situation, the 82385's "bus watching" mechanism preserves
cache coherency by monitoring the system bus address lines at no cost
to system or local throughput.
The 82385 is completely software transparent, protecting the integrity
of system software. High performance and board savings are achieved
because the 82385 integrates a cache directory and all cache
management logic on one chip.
1.0 82385 FUNCTIONAL OVERVIEW
Th~ 82385 Cache Controller is a high performance 32-bit peripheral for
Intel's 80386 microprocessor. This chapter provides an overview of
the 82385, and of the basic architecture and operation of an 80386/
82385 system.
1.1 82385 OVERVIEW
The main function of a cache memory system is to provide fast local
storage for frequently accessed code and data. The cache system
intercepts 80386 memory references to see if the required data resides
in the cache. If the data resides in the cache (a hit), it is returned
to the 80386 without incurring wait states. If the data is not cached
(a miss), the reference is forwarded to the system and the data
retrieved from main memory. An efficient cache will yield a high "hit
rate" (the ratio of cache hits to total 80386 accesses), such that the
majority of accesses are serviced with zero wait states. The net
effect is that the wait states incurred in a relatively infrequent
miss are averaged over a large number of accesses, resulting in an
average of nearly zero wait states per access. Since cache hits are
serviced locally, a processor operating out of its local cache has a
much lower "bus utilization" which reduces system bus bandwidth
requirements, making more bandwidth available to other bus masters.
The 82385 Cache Controller integrates a cache directory and all cache
management logic required to support an external 32 Kbyte cache. The
cache directory structure is such that the entire physical address
range of the 80386 (4 Gigabytes) is mapped into the cache. Provision
is made to allow areas of memory to be set aside a non-cacheable. The
user has two cache organization options: direct mapped and 2-way set
associative. Both provide the high hit rates necessary to make a
large, relatively slow main memory array look like a fast, zero wait
state memory to the 80386.
A good hit rate is an essential ingredient of a successful cache
implementation. Hit rate is the measure ,of how efficient a cache is
in maintaining a copy of the most frequently requested code and data.
However, efficiency is not the only factor for performance
consideration. Just as essential are sound cache management
policies. These policies refer to the handling of 80386 writes,
preservation of cache coherency, and ease of system design. The
82385's "posted write" capability allows 80386 memory writes,
including non-cacheable, to run with zero wait states, and the 82385's
"bus watching" mechanism preserves cache coherency with no impact on
system performance. Physically, the 82385 ties directly to the 80386
with virtually no external logic.
***Versions:...
***Features:...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**85C496/497 486-VIP 486 Green PC VESA/ISA/PCI Chipset <95
***Info:
The SiS 486-VIP (VESA/ISA/PCI) chips are two-chip solution ideally for
Intel's 80486, SL Enhanced 486, P24D/P24T/DX4 CPU, AMD's 486, Enhanced
Am486 and Cyrix's Cx486 (M7)/Cx 5x86 CPU based on green AT system. By
supporting the most popular industrial standard system interfaces, it
provides flexible configurations for system design and applications.
The SiS85C496 PCI & CPU Memory Controller (PCM) integrates the Host
Bridge (Host Interface), the cache and main memory DRAM Controller,
the PCI Bridge, the built-in IDE Controller, and the FS-Link Bus (Fast
Slow Link Bus). It provides the address paths and bus control for
transfers among the Host (CPU/L1 cache), main memory (L2 cache and
DRAM), the Peripheral Component Interconnect (PCI) Bus, and the
FS-Link Bus. The L2 cache controller supports both write-through and
write-back cache policies and cache sizes up to 1 MBytes. The cache
memory can be built using standard asynchronous SRAMs. The main
memory DRAM controller interfaces DRAM to the Host Bus, PCI Bus, and
FS-Link Bus. Up to eight single sided SIMMs or four double sided SIMMs
provide a maximum of 255 MBytes of main memory. The installation of
DRAM SIMMs is "Table-Free", which allows the SIMMs be installed into
any slot location and any combinations. The built-in IDE hard disk
controller allows CPU accessing hard disk and also provides higher
system integration with lower system cost. The 85C496 is intended to
be used with the SiS85C497 which is a AT Bus Controller with built-in
206 controller.
The SiS85C497 AT Bus Controller and Megacells (ATM) provides the
interface between PCI/CPU/Memory Bus (fast machine) and the ISA Bus
(slow machine). It also integrates many of the common I/O functions
in today's ISA based PC systems. The 85C497 comprises the FS-Link
interface (Fast-Slow Link interface), ISA bus controller , DMA
controller and data buffers to isolate the FS-Link Bus from the ISA
Bus and to enhance performance. It also integrates a 14 channel
edge/level interrupt controller, refresh controller, a 8-bit BIOS
timer, three programmable timer/counters, non-maskable-interrupt (NMI)
control logic, Power Management Unit, and RTC. Figure 1 .1 [see
datasheet] shows the system block diagram.
***Configurations:...
***Features:...
**85C501/502/503 Pentium/P54C PCI/ISA Chipset <01/09/95...
**5101/5102/5103 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5120 Pentium PCI/ISA Chipset (Mobile) <01/28/97...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5511/5512/5513 Pentium PCI/ISA <06/14/95...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
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