[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97
***Notes:...
***Info:
The Intel 380FB PCIset (380FB) consists of the 82380FB Mobile
PCI-to-PCI Bridge (MPCI2) and the 82380AB Mobile PCI-to-ISA Bridge
(MISA). The 380FB supports four PCI slots and three ISA slots. The
MPCI2 and MISA can also be used individually to provide either PCI
slot expansion or ISA slot expansion.
The 380FB supports a full Hot Docking capable docking station with 5V
PCI and ISA add-in expansion slots. MPCI2 provides the docking con-
trol for hot insertion, power management, and a PCI-to-PCI bridge to a
5V PCI desktop style add-in bus. Internal arbitration supports four
bus masters on the secondary PCI bus. The PC/PCI arbitration interface
logic provides PC/PCI bridge support. The 380FB controls all docking,
undocking and suspend/resume sequences for the docking station. The
EPROM interface logic provides an industry standard interface to a
non-volatile memory device (EPROM) for supporting dynamic
autoconfiguration of a previously configured notebook/docking station
combination. The Power management logic provides a control and status
interface between the docking station and notebook that allows the
docking station to control the state of the notebook. A non-volatile
memory interface is used to store docking identification and notebook
configuration information to speed dynamic configuration for a
pre-configured notebook docking combination.
MPCI2 supports the PCI bus enumeration mechanism for PCI-to-PCI
bridges. This is needed to support the Windows 95 dynamic
configuration of system resources when the system docks or
undocks. Otherwise, the operating system must reset the system after
reconfiguration. The undocking mechanism of the 380FB guarantees a
safe notebook removal. Event notification allows docking resources to
be dynamically removed and applications gracefully shut down, if
needed. A hardware mechanism is provided to indicate when the notebook
is prepared to undock. This can be used to eject or unlock the
notebook from the docking station.
The MPCI2’s subtractive decoding guarantees that all accesses targeted
for a downstream ISA bridge (such as the MISA) arrive at their
destination. Software does not need to determine the devices on the
ISA bridge and then program positive decode ranges (as is needed on
traditional positive decode bridges).
***Versions:...
***Features:...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C898 System/Power Management Controller (non-cache)c:Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:
o Processor interface:
- Intel 486SX, DX, DX2, SLe, DX4, P24T, P24D
- AMD 486DX, DX2, DXL, DXL2, Plus
- Cyrix DX, DX2, M7
- CPU frequencies supported 20, 25, 33, 40 and 50MHz
- Auto clock detection
o DRAM interface:
- Up to 128MB main memory support
- Supports 256KB, 1MB, 4MB, and 16MB single- and double-sided SIMM
modules
- Read page-hit timing of 3-2-2-2 at 33MHz
- Supports hidden, slow, and CAS-before-RAS refresh
- Eight RAS lines to support eight banks of DRAM
- Programmable wait states for DRAM reads and writes
- Enhanced DRAM configuration map
- Strong drive on MA lines (12/24mA)
- Supports asymmetric DRAMs
o Power management:
- Support for SMM (System Management Mode) for system power
management implementations
- Programmable power management
- Programmable wake-up events through hardware, software, and
external SMI source
- Multiple level GREEN support (NESTED_GREEN)
- STPCLK# protocol support
- Programmable GREEN event timer
o ISA interface:
- 100% IBM PC/AT ISA compatible
- Integrates DMA, timer, and interrupt controllers
- Optional PS/2 style IRQ1 and IRQ12 latching
o VESA VL interface:
- Conforms to the VESA V2.0 specification
- Optional support for up to two VL masters
o Miscellaneous features:
- Full support for shadow RAM, and write protection for video,
adapter, and system BIOS
- Enhanced arbitration scheme
- Transparent 8042 emulation for fast CPU Reset and Gate A20
generation
o Packaging:
- Higher integration
- Reduced TTL count
- Low-power, high-speed 0.8-micron CMOS technology
- 208-pin PQFP (Plastic Quad Flat Pack)
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved