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**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97
***Notes:...
***Info:
The Intel 380FB PCIset (380FB) consists of the 82380FB Mobile
PCI-to-PCI Bridge (MPCI2) and the 82380AB Mobile PCI-to-ISA Bridge
(MISA). The 380FB supports four PCI slots and three ISA slots. The
MPCI2 and MISA can also be used individually to provide either PCI
slot expansion or ISA slot expansion.
The 380FB supports a full Hot Docking capable docking station with 5V
PCI and ISA add-in expansion slots. MPCI2 provides the docking con-
trol for hot insertion, power management, and a PCI-to-PCI bridge to a
5V PCI desktop style add-in bus. Internal arbitration supports four
bus masters on the secondary PCI bus. The PC/PCI arbitration interface
logic provides PC/PCI bridge support. The 380FB controls all docking,
undocking and suspend/resume sequences for the docking station. The
EPROM interface logic provides an industry standard interface to a
non-volatile memory device (EPROM) for supporting dynamic
autoconfiguration of a previously configured notebook/docking station
combination. The Power management logic provides a control and status
interface between the docking station and notebook that allows the
docking station to control the state of the notebook. A non-volatile
memory interface is used to store docking identification and notebook
configuration information to speed dynamic configuration for a
pre-configured notebook docking combination.
MPCI2 supports the PCI bus enumeration mechanism for PCI-to-PCI
bridges. This is needed to support the Windows 95 dynamic
configuration of system resources when the system docks or
undocks. Otherwise, the operating system must reset the system after
reconfiguration. The undocking mechanism of the 380FB guarantees a
safe notebook removal. Event notification allows docking resources to
be dynamically removed and applications gracefully shut down, if
needed. A hardware mechanism is provided to indicate when the notebook
is prepared to undock. This can be used to eject or unlock the
notebook from the docking station.
The MPCI2’s subtractive decoding guarantees that all accesses targeted
for a downstream ISA bridge (such as the MISA) arrive at their
destination. Software does not need to determine the devices on the
ISA bridge and then program positive decode ranges (as is needed on
traditional positive decode bridges).
***Versions:...
***Features:...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C802G/GP System/Power Management Controller (cached) c:93
***Notes:...
***Info:...
***Configurations:...
***Features:
[features found only in the 802GP are marked in [] brackets ]
o Processor interface:
- Intel 80486SX, DX, DX2, SLe, DX4, P24T, P24D
- AMD 486SX, DX2, DXL, DXL2, Plus
- Cyrix DX, DX2, M7
- CPU frequencies supported 20, 25, 33, 40 and 50MHz
o Cache interface:
- Direct mapped cache
- Two banks interleaved or single bank non-interleaved
- 64, 128, 256 and 512K cache sizes
- Programmable wait states for L2 cache reads and writes
- 2-1-1-1 read burst and zero wait state write @ 33MHz
- No Valid bit required
[- Supports external single-chip cache modules from thyroid-party ]
[ vendors for high performance at 50MHz ]
- Supports CPUs with L1 write-back support
o DRAM interface:
- Up to 128MB main memory support
- Supports 256KB, 1MB, 4MB, and 16MB single- and double-sided SIMM
modules
- Read page hit timing of 3-2-2-2 at 33MHz
- Supports hidden, slow. and CAS-before-RAS refresh
- Four RAS lines to support four banks of DRAM
[- Eight RAS lines to support four banks of DRAM ]
- Programmable wait states for DRAM reads and writes
[- Programmable memory holes for supporting ISA memory ]
- Enhanced DRAM configuration map
[- Strong drivers on the MA lines (12/24mA) ]
[- Supports asymmetric DRAMs ]
o Power management:
- Support for SMM (System Management Mode) for system power
management implementations
- Programmable power management
[- CPU clock control ]
- Programmable wake-up events through hardware, software, and
external SMI source
- Multiple level GREEN support (NESTED_GREEN)
- STPCLK# protocol support
[- Programmable GREEN event timer ](802G only)
[- Individually programmable peripheral ](802GP only)
o ISA interface:
- 100% IBM PC/AT ISA compatible
[- Programmable edge- or level-trigger interrupts ]
- integrates DMA, timer and interrupt controllers
[- Slew rate control for output drivers ]
- Optional PS/2 style IRQ1 and IRQ12 latching
o VESA VL interface:
- Conforms to the VESA V2.0 specification
- Optional support for up to two VL masters
o Miscellaneous features: (802G only)
- Full support for shadow RAM, write protection, L1/L2
cacheability for video, adapter, and system BIOS
- Enhanced arbitration scheme
- Transparent 8042 emulation for fast CPU reset and GATEA20
generation
o [Miscellaneous features: ](802GP only)
[- Full support for flash, write protection, L1/L2 ]
[ cacheability for video, adapter, and system BIOS ]
[- Provides Micro Channel bridge support ]
[- 10-/16-nit I/O decodes ]
[- Enhanced arbitration scheme ]
o Packaging:
- Higher integration
- Reduced TTL count
- Low-power, high~speed 0.8-micron CMOS technology
- 208-pin PQFP (Plastic Quad Flat Pack)
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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