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**82380FB/AB  PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97
***Notes:...
***Info:
The  Intel  380FB  PCIset  (380FB)  consists  of  the  82380FB  Mobile
PCI-to-PCI  Bridge (MPCI2)  and the  82380AB Mobile  PCI-to-ISA Bridge
(MISA). The  380FB supports  four PCI slots  and three ISA  slots. The
MPCI2 and  MISA can  also be used  individually to provide  either PCI
slot expansion or ISA slot expansion.

The 380FB supports a full  Hot Docking capable docking station with 5V
PCI and ISA  add-in expansion slots.  MPCI2 provides  the docking con-
trol for hot insertion, power management, and a PCI-to-PCI bridge to a
5V PCI  desktop style add-in  bus. Internal arbitration  supports four
bus masters on the secondary PCI bus. The PC/PCI arbitration interface
logic provides PC/PCI bridge  support. The 380FB controls all docking,
undocking and  suspend/resume sequences for the  docking station.  The
EPROM  interface logic provides  an industry  standard interface  to a
non-volatile   memory   device    (EPROM)   for   supporting   dynamic
autoconfiguration of a  previously configured notebook/docking station
combination. The Power management  logic provides a control and status
interface  between the docking  station and  notebook that  allows the
docking station to control the  state of the notebook.  A non-volatile
memory interface is used  to store docking identification and notebook
configuration  information  to   speed  dynamic  configuration  for  a
pre-configured notebook docking combination.

MPCI2  supports  the  PCI  bus enumeration  mechanism  for  PCI-to-PCI
bridges.   This   is  needed  to   support  the  Windows   95  dynamic
configuration   of  system   resources  when   the  system   docks  or
undocks. Otherwise, the  operating system must reset  the system after
reconfiguration.  The  undocking mechanism  of the 380FB  guarantees a
safe notebook removal. Event  notification allows docking resources to
be  dynamically  removed and  applications  gracefully  shut down,  if
needed. A hardware mechanism is provided to indicate when the notebook
is  prepared to  undock.  This  can  be used  to eject  or unlock  the
notebook from the docking station.

The MPCI2’s subtractive decoding guarantees that all accesses targeted
for  a  downstream ISA  bridge  (such as  the  MISA)  arrive at  their
destination. Software  does not need  to determine the devices  on the
ISA bridge  and then program positive  decode ranges (as  is needed on
traditional positive decode bridges).

***Versions:...
***Features:...
**82384       Clock Generator and Reset Interface                  c86...
**82385       32-bit Cache Controller for 80386               09/29/87...
**82385SX     32-bit Cache Controller for 80386SX             01/25/89...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT18          80386SX Single Chip                            c:Sep91
***Info:...
***Configurations:...
***Features:
o   Highly Integrated, Single Chip 80386SX AT Compatible Solution
o   Special Multiple Context Hardware EMS Support (LIM 4.0 compatible) 
    using 2 sets of 32 EMS Registers
o   Single or Dual BIOS
o   Shadow RAM support over entire C0000 to DFFFF Address range in 16K 
    increments, E0000 to FFFFF in 64K increments
o   Page Mode and 2-way Interleaving
o   Supports up to 12MHz AT Bus Clock
o   High Performance Muxed DRAM Interleave
o   Programmable DRAM timing
o   Asynchronous AT Bus Clock
o   Three-State Test Mode
o   16-Bit ROM BIOS Support

HT 18A/B Special Features
o   16 and 20 MHz CPU Clock Speeds
o   Supports up to 8M CPU Memory using combinations of 64K, 256K and 
    1M Devices
o   4 Bank, 4-way Interleave Mode

HT18C/25MHz Special Features
o   16, 20 and 25MHz CPU Clock Speeds
o   Supports up to 20M with EMS CPU Memory using combinations of 256K, 
    1M and 4M Devices

**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
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*Unresearched:...
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