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**82379AB System I/O-APIC (SIO.A) <Dec94
***Notes:...
***Info:
The 82379AB System I/O-APIC (SIO.A) component provides the bridge
between the PCI bus and the ISA expansion bus. The 82379AB also
integrates many of the common I/O functions found in today's ISA based
PC systems. The 82379AB incorporates the logic for a PCI interface
(master and slave), ISA interface (master and slave), enhanced seven
channel DMA controller that supports data buffers to isolate the PCI
bus from the ISA bus and to enhance performance, PCI and ISA
arbitration, 14 level interrupt controller, a 16-bit BIOS timer, three
programmable timer/counters, and Non-Maskable Interrupt (NMI) Control
Logic. The 82379AB also provides decode for peripheral devices such as
the Flash BIOS, Real Time Clock, Keyboard/Mouse Controller, Floppy
Controller, two Serial Ports, one Parallel Port, and IDE Hard Disk
Drive. The 82379AB supports several Advanced Power Management features
such as SMI# Interrupt. The 82379AB also supports a total of 6 PCI
Masters, and can support up to 4 PCI Interrupts. The 82379AB
incorporates an Advanced Programmable Interrupt Controller (APIC) that
communicates with the processor via a dedicated two data bit bus.
***Versions:...
***Features:...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:
The Intel 82495XP cache controller and 82490XP cache RAM, when coupled
with a user-implemented memory bus controller, provide a second-level
cache subsystem that eliminates the memory latency and bandwidth
bottleneck for a wide range of multiprocessor systems based on the
i860 XP microprocessor. The CPU interface is optimized to serve the
i860 XP microprocessor with zero wait states at up to 50 MHz. A
secondary cache built from the 82495XP and 82490XP isolates the CPU
from the memory subsystem; the memory can run slower and follow a
different protocol than the i860 XP microprocessor.
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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*HMC (Hulon Microelectronics)...
*Logicstar...
**SL9250 Page Mode Memory Controller (16/20MHz 8MB Max) <oct88
***Info:...
***Versions:...
***Features:...
**SL9350 Page Mode Memory Controller (16/20/25MHz 16MB Max) <oct88...
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