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*_IBM...
*ACC Micro...
**ACC2020    Power Management Chip                                 c92
***info:...
***Versions:...
***Features:
o   Provides eight trigger input channels for monitoring activities 
    such as keyboard, video, hard disk, floppy disk, and user defined 
    device.
o   Provides eight power control outputs
o   Each power control output status can be determined by the 
    combinations of the eight trigger inputs
o   Provides eight user programmable time-out timers.
o   Flexible timer scales:
      2 timers from 1/8 second to 14 seconds
      4 timers from 1 minute to 15 minutes
      1 timer from 2 minutes to 210 minutes
      1 timer from 4 minutes to 7 hours
o   Each trigger input can select one of the two timer scales
o   No glitch CPU clock switching functions
o   Supports CPU clock up to 66 MHz
o   Generates 16 MHz clock for AT Bus
o   Generates 32.768 KHz for both RTC and Ao02020 by using 32.768 KHz 
    crystal
o   Supports Modem ring power-on
o   Supports scheduled power-on
o   Supports cover switch power-down/on
o   Supports Suspend and Resume
o   Provides six operation modes:
      Full Operation mode
      Rest mode
      Standby mode
      Shutdown mode
      Freeze mode
      Off mode
o   Predefined mode transition among Normal Rest. and Standby modes
o   Programmable transitions of operation modes
o   Provides interrupt request for suspend resume operation
o   Interrupt request output can be masked
o   Supports Programmable Slow Refresh in Shutdown and Freeze modes
o   Supports CAS before RAS refresh
o   80-pin QFP

**ACC5500    Multifunction I/O Control Chip for PS2 Model 50/60    c88...
**
**Other chips...
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*AMD . . . . . . . [no datasheets, some info]...
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*Contaq  . . . . . [no datasheets, some info]...
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*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor  to form a CPU Cache chip  set designed for high
performance  servers  and   function-rich  desktops.  The  high  speed
interconnect between  the CPU and cache components  has been optimized
to  provide zero-wait  state operation.   This CPU  Cache chip  set is
fully compatible  with existing software,  and has new  data integrity
features for mission critical applications.

The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82496  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit  wide memory bus widths,  16, 32, and 64  byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82491, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92
***Notes:...
***Info:...
***Configurations:...
***Features:...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
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