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**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97
***Notes:...
***Info:...
***Versions:...
***Features:
o Supported Kits for both Pentium and Pentium II Microprocessors
- 82430TX ISA Kit
- 82440LX ISA/DP Kit
o Multifunction PCI to ISA Bridge
- Supports PCI at 30 MHz and 33 MHz
- Supports PCI Rev 2.1 Specification
- Supports Full ISA or Extended I/O (EIO) Bus
- Supports Full Positive Decode or Subtractive Decode of PCI
- Supports ISA and EIO at 1/4 of PCI Frequency
o Supports both Mobile and Desktop Deep Green Environments
- 3.3V Operation with 5V Tolerant Buffers
- Ultra-low Power for Mobile Environments Support
- Power-On Suspend, Suspend to RAM, Suspend to Disk, and Soft-
OFF System States
- All Registers Readable and Restorable for Proper Resume
from 0.V Suspend
o Power Management Logic
- Global and Local Device Management
- Suspend and Resume Logic
- Supports Thermal Alarm
- Support for External Microcontroller
- Full Support for Advanced Configuration and Power Interface
(ACPI) Revision 1.0 Specification and OS Directed Power
Management
o Integrated IDE Controller
- Independent Timing of up to 4 Drives
- PIO Mode 4 and Bus Master IDE Transfers up to 14 Mbytes/sec
- Supports "Ultra DMA/33" Synchronous DMA Mode Transfers up to
33 Mbytes/sec
- Integrated 16 x 32-bit Buffer for IDE POI Burst Transfers
- Supports Glue-less "Swap-Bay" Option with Full Electrical
Isolation
o Enhanced DMA Controller
- Two 82C37 DMA Controllers
- Supports PCI DMA with 3 PC/PCI Channels and Distributed DMA
Protocols (Simultaneously)
- Fast Type-F DMA for Reduced PCI Bus Usage
o Interrupt Controller Based on Two 82C59
- 15 Interrupt Support
- Independently; Programmable for Edge/Level Sensitivity
- Supports Optional I/O APIC
- Serial Interrupt Input
o Timers Based on 82C54
- System Timer, Refresh Request, Speaker Tone Output
o USB
- Two USB 1.0 Ports for Serial Transfers at 12 or 1.5 Mbit/sec
- Supports Legacy Keyboard and Mouse Software with USB-based
Keyboard and Mouse
- Supports UHCI Design Guide
o SMBus
- Host Interface Allows CPU to Communicate Via SMBus
- Slave Interface Allows External SMBus Master to Control
Resume Events
o Real-Time Clock
- 256-byte Battery-Back CMOS SRAM
- Includes Date Alarm
- Two 8-byte Lockout Ranges
o Microsoft Win95 Compliant
o 324 mBGA Package
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HT18 80386SX Single Chip c:Sep91
***Info:
The HT18 is an advanced PC/AT compatible, single-chip 80386SX design
solution. This highly integrated single chip allows simple, low cost
system design options while featuring high performance, low power
consumption, and minimum board space requirements. Advanced memory
management features include support for page mode, with 2 or 4-way
interleaving in both pipelined and non-pipelined modes(18A/B only).
Extended Hardware EMS options include dual sets of 32 registers with
multiple context operation. Revisions A/B support 256K and 1M DRAMs in
1 by 1, 1 by 4, and 1 by 9 device configurations. Rev C supports 4M
devices, as well. A Shadow RAM option for System Video BIOS and dual
or single system ROM BIOS support adds to overall design versatility.
A complete PC/AT compatible system with advanced features may be
implemented with minimal external support logic. The HT18 performs all
CPU and peripheral support functions in a single chip. Integrated
device functions include DMA Controllers, a Memory Mapper, Timers,
Counters, Interrupt Controllers, a Bus Controller and all supporting
circuitry for PC core logic requirements. An asynchronous AT Bus clock
allows for a constant 8MHz Bus clock rate for highest bus device
compatibility as defined in IEEE Spec P996. This device is packaged in
a 208-pin Plastic Quad Flat Pack combining several external buffers
into this space saving solution.
***Configurations:...
***Features:...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
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