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**82371MX     Mobile PCI I/O IDE Xcelerator (MPIIX)           11/01/95
***Notes:...
***Info:
The 82371MX PCI I/O IDE Xcelerator (MPIIX) provides the bridge between
the PCI bus and the  ISA-like Extended I/O expansion bus. In addition,
the  82371MX  has an  IDE  interface  that  supports two  IDE  devices
providing  an interface  for IDE  hard disks  and CD  ROMS.  The MPIIX
integrates many common  I/O functions found in ISA  based PC systems-a
seven-channel DMA controller, two 82C59 interrupt controllers. an 8254
timer/counter, Intel  SMM power management support,  and control logic
for NMI  generation. Chip select  decoding is provided for  BIOS, real
time  clock,  and   keyboard  controller.  Edge/Level  interrupts  and
interrupt steering are supported for PCI plug and play compatibility.

The MPIIX also  provides the Extended I/O Bus  for a direct connection
to  Super   I/O  devices   providing  a  complete   PC-compatible  I/O
solution.  MPIIX also  provides support  for the  “Mobile  PC/PCI" DMA
Expansion protocol that enables the implementation of Docking Stations
with  full ISA and  PCI capability  without running  the full  ISA bus
across   the   docking    connector.   For   motherboard   Plug-n-Play
compatibility.   the  82371MX  also   provides  three   steerable  DMA
channels. up  to three steerable  interrupt lines, and  a programmable
chip select. The interrupt lines can be routed to any of the available
ISA interrupts.

The MPIIX’s power management function supports SMI# interrupt sources,
extensive clock control  (including Auto Clock Throttling), peripheral
power  idle detection  with access  traps. system  Suspend-to-DRAM and
Suspend-to-Disk.

***Versions:...
***Features:...
**82371AB     PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4)     02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB)   c:Mar93...
**82378       System I/O (SIO) (82378IB and 82378ZB)           c:Mar93...
**82379AB     System I/O-APIC (SIO.A)                           <Dec94...
**82380       32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB  PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384       Clock Generator and Reset Interface                  c86...
**82385       32-bit Cache Controller for 80386               09/29/87...
**82385SX     32-bit Cache Controller for 80386SX             01/25/89...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:
***440FX (Natoma)       05/06/96...
***440LX (Balboa)       08/27/97...
***440BX (Seattle)      c:Apr'98...
***440DX (?)            c:?...
***440EX (?)            c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?)          05/17/99...
***440MX (Banister)     05/17/99...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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**SL82C550   'Rossini' Pentium          [no datasheet]            c:95
***Notes:
from:
http://www.os2forum.or.at/english/info/os2hardwareinfo/pci_chips.html

The Symphony  "Rossini" Chipset  (Symphony Labs:  10AD/4269) (9/13/95)
This is apparently a low-cost alternative to the Triton chipset, as it
operates  with up  to 66  MHz external  clock rates,  up to  two CPUs,
pipelined or non-pipelined, synchronous or [conventional] asynchronous
SRAM cache,  EDO RAM, and  does dual-port busmastering IDE.   It will,
apparently, adjust the voltages to  its various (CPU, PCI, cache, RAM)
buses  to suit  their requirements,  and will  control up  to six  PCI
masters.   It consists  of the  SL82C551 cache/memory  controller, the
SL82C522 data path controller, and the SL82C555 system I/O controller.

***Configurations:...
**
**Support Chips:
**SL82C365    Cache Controller (for 386DX/SX)                     c:91...
**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
*TI (Texas Instruments)...
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*Unresearched:...
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*Winbond...
*ZyMOS...
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