[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95
***Notes:...
***Info:...
***Versions:...
***Features:
o Provides a Bridge Between the PCI Bus and Extended I/O Bus
- PCI Bus; 25-33 MHz
- Extended I/O Bus; 7.5-8.33 MHz
o System Power Management (Intel SMM Support)
- Programmable System Management Interrupt (SMI)-Hardware/Software
Events, EXTSMI#
- Programmable CPU Clock Control (STPCLK#) with Auto Clock
Throttle
- Peripheral Device Power Management (Local Standby)
- Suspend State Support (Suspend-to-DRAM and Suspend-to-Disk)
o Enhanced DMA Functions
- Two 8237 DMA Controllers
- Fast Type F DMA
- Compatible DMA Transfers
- PC/PCI DMA Expansion for Docking Support
o Fast IDE Interface
- PIO Mode 4 Transfers
- 2x16-Bit Posted Write Butter and 1x32-Bit Read Prefetch Buffer
o Plug-n-Play Port for Motherboard Devices
- 3 Steerable DMA Channels
- 1 Steerable Interrupt Lane (Plus 2 Steerable PCI Interrupts)
- 1 Programmable Chip Select
o Functionality of One 82C54 Timer
- System Timer
- Refresh Request
- Speaker Tone Output
o Functionality of Two 82C59 Interrupt Controllers
- 14 Interrupts Supported
- Independently Programmable for Edge/Level Sensitivity
o X-Bus Peripheral Support
- Chip Select Decode
- Controls Lower X-Bus Data Byte Transceiver
o Non-Maskable Interrupts (NMI)
- PCI System Error Reporting
o NAND Tree for Board-Level ATE Testing
o 176-Pin TOFP
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C895 System/Power Management Controller (cached) c:Sep94
***Notes:...
***Info:
Overview
The 82C895 provides a highly integrated solution for fully compatible,
high performance PC/AT platforms. This chipset will support 486SX/
DX/DX2/DX4 and P24T microprocessors in the most cost effective and
power efficient designs available today. For power users, this
chipset offers optimum performance for systems running up to 50MHz.
Based fundamentally on OPTi's proven 82C801 and 82C802 design
architectures, the 82C895 adds additional memory configurations and
extensive power management control for the processor and other
motherboard components.
The 820895 supports the latest write-back processor designs from
Intel, AMD, and Cyrix, as well as supporting the AT bus and VESA local
bus for compatibility and performance. It also includes an
82C206-compatible Integrated Peripherals Controller (IPC). all in a
single 208-pin PQFP (Plastic Quad Flat Pack) package for low cost.
2.1 Power Management
This block diagram [see datasheet] exemplifies the flexibility of the
82C895/82C602 GREEN strategy. System designs can easily accommodate
both SLe and non-SLe CPUs. If an Intel non-SLe CPU is used, SMI#,
SMIACT#, and FLUSH# are no connects. One design can easily accomm-
odate both types of processors with minimal changes for upgrades.
***Configurations:...
***Features:...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved