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**82371FB/SB  PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95
***Notes:...
***Info:...
***Versions:...
***Features:
o   Bridge Between the PCI Bus and ISA Bus
o   PCI and ISA Master/Slave Interface
    - PCI from 25-33 MHz
    - ISA from 7.5-8.33 MHz
    - 5 ISA Slots
o   Fast IDE Interface
    - Supports PIO and Bus Master IDE
    - Supports up to Mode 4 Timings
    - Transfer Rates to 22 MB/Sec
    - 8 x 32-Bit Buffer for Bus Master IDE PCI Burst Transfers
    - Separate Master/Slave IDE Mode Support (PIIX3)            
o   Plug-n-Play Port for Motherboard Devices
    - 2 Steerable DMA Channels (PIIX Only)
    - Fast DMA with 4-Byte Buffer (PIIX Only)
    - 2 Steerable Interrupts Lines on the PIIX and 1 Steerable 
      Interrupt Line on the PIIXS
    - 1 Programmable Chip Select
o   Steerable PCI Interrupts for PCI Device Plug-n-Play
o   PCI Specification Revision 2.1 Compliant (PIIX3)
o   Functionality of One 82C54 Timer
    - System Timer; Refresh Request; Speaker Tone Output
o   Two 82C59 Interrupt Controller Functions
    - 14 Interrupts Supported
    - Independently Programmable for Edge/Level Sensitivity
o   Enhanced DMA Functions
    - Two 8237 DMA Controllers
    - Fast Type F DMA
    - Compatible DMA Transfers
    - 7 Independently Programmable Channels
o   X-Bus Peripheral Support
    - Chip Select Decode
    - Controls Lower X-Bus Data Byte Transceiver
o   I/O Advanced Programmable Interrupt Controller (IOAPIC) Support 
    (PIIX3)
o   Universal Serial Bus (USB) Host Controller (PIIX3)
    - Compatible with Universal Host Controller Interface (UHCI)
    - Contains Root Hub with 2 USB Ports
o   System Power Management (Intel SMM Support)
    - Programmable System Management Interrupt (SMI)-Hardware Events,
      Software Events, EXTSMI#
    - Programmable CPU Clock Control (STPCLK#)
    - Fast On/Off Mode
o   Non-Maskable Interrupts (NMI)
    - PCI System Error Reporting
o   NAND Tree for Board-Level ATE Testing
o   208-Pin QFP

**82371MX     Mobile PCI I/O IDE Xcelerator (MPIIX)           11/01/95...
**82371AB     PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4)     02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB)   c:Mar93...
**82378       System I/O (SIO) (82378IB and 82378ZB)           c:Mar93...
**82379AB     System I/O-APIC (SIO.A)                           <Dec94...
**82380       32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB  PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384       Clock Generator and Reset Interface                  c86...
**82385       32-bit Cache Controller for 80386               09/29/87...
**82385SX     32-bit Cache Controller for 80386SX             01/25/89...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT44          Secondary Cache                                c:Jun92
***Info:
The  HT44 is  a  look-aside write-through,  80486SX,  486DX or  486DX2
secondary cache  controller. It is  packaged in an  inexpensive 84-pin
plastic-leaded chip carrier (PLCC).

Architecture
With  its look-aside architecture,  the HT44  fits beside  the CPU-to-
Memory bus  and not in  the data path.   Therefore, once the  HT44 has
been designed  into a  486 system, it  can be populated  for secondary
cache systems or left vacant for non-secondary cache systems. The HT44
is direct-mapped to the available address space.

Performance
The  HT44  has a  number  of  performance  enhancing features.   These
include zero-waitstate burst line fills  to the 486 on secondary cache
hits, and simultaneous 486 and secondary cache updates on read misses.

Memory Configurations
The HT44 supports  cache sizes from 32KBytes to  1MB. Both synchronous
and asynchronous  SRAMs are supported.  25ns SRAMs are  sufficient for
zero-wait-state operation at 33MHz.

Chip Set Support
The HT44 can,  be implemented with minimal glue logic  in a 486 system
with the  HTK340 (code  name Shasta) chip  set.  The registers  in the
HTK340  allow  for programming  of  non-cacheable and  write-protected
areas of  memory. The  HTK340 will support  the HT44  with synchronous
SRAMs only.   Future Headland chip sets will  support both synchronous
and asynchronous SRAM designs.

The HT44  can also be used  with some third-party  chip sets, however,
additional glue logic may be required.

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