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**82371FB/SB  PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95
***Notes:...
***Info:
The 82371FB  (PIIX) and  82371SB (PIIXS) PCI  ISA IDE  Xcelerators are
multi-function PCI  devices implementing a  PCI-to-ISA bridge function
and an PCI IDE function. In addition, the PIIXS implements a Universal
Serial Bus  host/hub function. As a PCI-to-ISA  bridge, the PIIX/PIIX3
integrates many  common I/O functions found in  ISA-based PC systems-a
seven-channel DMA controller, two 82059 interrupt controllers, an 8254
timer/counter, and power management support. In addition to compatible
transfers, each  DMA channel supports  type F transfers.   Chip select
decoding  is  provided  for   BIOS,  real  time  clock,  and  keyboard
controller. Edge/Level interrupts and interrupt steering are supported
for PCI plug  and play compatibility. The PIIX/PIIX3  supports two IDE
connectors for up  to four IDE devices providing  an interface for IDE
hard disks and  CD ROMS. The PIIX/PIIX3 provides  motherboard plug and
play  compatibility.   PIIX  implements  two  steerable  DMA  channels
(including  type  F  transfers)  and  up to  two  steerable  interrupt
lines. PIIX3  implements one steerable interrupt  line.  The interrupt
lines  can be  routed to  any of  the available  ISA  interrupts. Both
PIIX/PIIX3 implement a programmable chip select.

PIIXS contains  a Universal Serial  Bus (USB) Host Controller  that is
UHCI compatible.  The Host Controller’s root hub  has two programmable
USB ports. PIIXS also provides support for an external IOAPIC.

----------------------------------------------------------------------
 This  document  describes   the  PIIXS  Component.   Unshaded  areas
 describe the  82371FB PIIX.  Shaded  areas, like this  one, describe
 the PIIXS operations that differ from the 82371FB PIIX.
----------------------------------------------------------------------
***Versions:...
***Features:...
**82371MX     Mobile PCI I/O IDE Xcelerator (MPIIX)           11/01/95...
**82371AB     PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4)     02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB)   c:Mar93...
**82378       System I/O (SIO) (82378IB and 82378ZB)           c:Mar93...
**82379AB     System I/O-APIC (SIO.A)                           <Dec94...
**82380       32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB  PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384       Clock Generator and Reset Interface                  c86...
**82385       32-bit Cache Controller for 80386               09/29/87...
**82385SX     32-bit Cache Controller for 80386SX             01/25/89...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT44          Secondary Cache                                c:Jun92
***Info:
The  HT44 is  a  look-aside write-through,  80486SX,  486DX or  486DX2
secondary cache  controller. It is  packaged in an  inexpensive 84-pin
plastic-leaded chip carrier (PLCC).

Architecture
With  its look-aside architecture,  the HT44  fits beside  the CPU-to-
Memory bus  and not in  the data path.   Therefore, once the  HT44 has
been designed  into a  486 system, it  can be populated  for secondary
cache systems or left vacant for non-secondary cache systems. The HT44
is direct-mapped to the available address space.

Performance
The  HT44  has a  number  of  performance  enhancing features.   These
include zero-waitstate burst line fills  to the 486 on secondary cache
hits, and simultaneous 486 and secondary cache updates on read misses.

Memory Configurations
The HT44 supports  cache sizes from 32KBytes to  1MB. Both synchronous
and asynchronous  SRAMs are supported.  25ns SRAMs are  sufficient for
zero-wait-state operation at 33MHz.

Chip Set Support
The HT44 can,  be implemented with minimal glue logic  in a 486 system
with the  HTK340 (code  name Shasta) chip  set.  The registers  in the
HTK340  allow  for programming  of  non-cacheable and  write-protected
areas of  memory. The  HTK340 will support  the HT44  with synchronous
SRAMs only.   Future Headland chip sets will  support both synchronous
and asynchronous SRAM designs.

The HT44  can also be used  with some third-party  chip sets, however,
additional glue logic may be required.

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