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**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95
***Notes:...
***Info:
The 82371FB (PIIX) and 82371SB (PIIXS) PCI ISA IDE Xcelerators are
multi-function PCI devices implementing a PCI-to-ISA bridge function
and an PCI IDE function. In addition, the PIIXS implements a Universal
Serial Bus host/hub function. As a PCI-to-ISA bridge, the PIIX/PIIX3
integrates many common I/O functions found in ISA-based PC systems-a
seven-channel DMA controller, two 82059 interrupt controllers, an 8254
timer/counter, and power management support. In addition to compatible
transfers, each DMA channel supports type F transfers. Chip select
decoding is provided for BIOS, real time clock, and keyboard
controller. Edge/Level interrupts and interrupt steering are supported
for PCI plug and play compatibility. The PIIX/PIIX3 supports two IDE
connectors for up to four IDE devices providing an interface for IDE
hard disks and CD ROMS. The PIIX/PIIX3 provides motherboard plug and
play compatibility. PIIX implements two steerable DMA channels
(including type F transfers) and up to two steerable interrupt
lines. PIIX3 implements one steerable interrupt line. The interrupt
lines can be routed to any of the available ISA interrupts. Both
PIIX/PIIX3 implement a programmable chip select.
PIIXS contains a Universal Serial Bus (USB) Host Controller that is
UHCI compatible. The Host Controller’s root hub has two programmable
USB ports. PIIXS also provides support for an external IOAPIC.
----------------------------------------------------------------------
This document describes the PIIXS Component. Unshaded areas
describe the 82371FB PIIX. Shaded areas, like this one, describe
the PIIXS operations that differ from the 82371FB PIIX.
----------------------------------------------------------------------
***Versions:...
***Features:...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HT18 80386SX Single Chip c:Sep91
***Info:
The HT18 is an advanced PC/AT compatible, single-chip 80386SX design
solution. This highly integrated single chip allows simple, low cost
system design options while featuring high performance, low power
consumption, and minimum board space requirements. Advanced memory
management features include support for page mode, with 2 or 4-way
interleaving in both pipelined and non-pipelined modes(18A/B only).
Extended Hardware EMS options include dual sets of 32 registers with
multiple context operation. Revisions A/B support 256K and 1M DRAMs in
1 by 1, 1 by 4, and 1 by 9 device configurations. Rev C supports 4M
devices, as well. A Shadow RAM option for System Video BIOS and dual
or single system ROM BIOS support adds to overall design versatility.
A complete PC/AT compatible system with advanced features may be
implemented with minimal external support logic. The HT18 performs all
CPU and peripheral support functions in a single chip. Integrated
device functions include DMA Controllers, a Memory Mapper, Timers,
Counters, Interrupt Controllers, a Bus Controller and all supporting
circuitry for PC core logic requirements. An asynchronous AT Bus clock
allows for a constant 8MHz Bus clock rate for highest bus device
compatibility as defined in IEEE Spec P996. This device is packaged in
a 208-pin Plastic Quad Flat Pack combining several external buffers
into this space saving solution.
***Configurations:...
***Features:...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
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