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**82370 Integrated System Peripheral (for 82376) c:Oct88
***Notes:...
***Info:
The 82370 is a multi-function support peripheral that integrates
system functions necessary in an 80376 environment. It has eight
channels of high performance 32-bit DMA (32-bit internal, 16-bit
external) with the most efficient transfer rates possible on the 80376
bus. System support peripherals integrated into the 82370 provide
Interrupt Control, Timers, Wait State generation, DRAM Refresh
Control, and System Reset logic.
The 82370's DMA Controller can transfer data between devices of
different data path widths using a single channel. Each DMA channel
operates independently in any of several modes; Each channel has a
temporary data storage register for handling non-aligned data without
the need for external alignment logic.
1.0 FUNCTIONAL OVERVIEW
The 82370 contains several independent functional modules. The
following is a brief discussion of the components and features of the
82370. Each module has a corresponding detailed section later in this
data sheet. Those sections should be referred to for design and
programming information.
1.1 82370 Architecture
The 82370 is comprised of several computer system functions that are
normally found in separate LSI and VLSI components. These include: a
high-performance, eight-channel, 32-bit Direct Memory Access
Controller; a 20-level Programmable Interrupt Controller which is a
superset of the 82C5SA; four 16-bit Programmable Interval Timers which
are functionally equivalent to the 82C54 timers; DRAM Refresh
Controller; a Programmable Wait State Generator; and system reset
logic. The interface to the 82370 is optimized for high-performance
operation with the 80376 microprocessor.
The 82370 operates directly on the 80376 bus. In the Slave Mode, it
monitors the state of the processor at all times and acts or idles
according to the commands of the host. It monitors the address
pipeline status and generates the programmed number of wait states for
the device being accessed. The 82370 also has logic to the reset of
the 80376 via hardware or software reset requests and processor
shutdown status.
After a system reset, the 82370 is in the Slave Mode. It appears to
the system as an I/O device. It becomes a bus master when it is
performing DMA transfers.
To maintain compatibility with existing software, the registers within
the 82370 are accessed as bytes. If the internal logic of the 82370
requires a delay before another access by the processor, wait states
are automatically inserted into the access cycle. This allows the
programmer to write initialization routines, etc. without regard to
hardware recovery times.
***Versions:...
***Features:...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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*OPTi...
**82C895 System/Power Management Controller (cached) c:Sep94
***Notes:...
***Info:
Overview
The 82C895 provides a highly integrated solution for fully compatible,
high performance PC/AT platforms. This chipset will support 486SX/
DX/DX2/DX4 and P24T microprocessors in the most cost effective and
power efficient designs available today. For power users, this
chipset offers optimum performance for systems running up to 50MHz.
Based fundamentally on OPTi's proven 82C801 and 82C802 design
architectures, the 82C895 adds additional memory configurations and
extensive power management control for the processor and other
motherboard components.
The 820895 supports the latest write-back processor designs from
Intel, AMD, and Cyrix, as well as supporting the AT bus and VESA local
bus for compatibility and performance. It also includes an
82C206-compatible Integrated Peripherals Controller (IPC). all in a
single 208-pin PQFP (Plastic Quad Flat Pack) package for low cost.
2.1 Power Management
This block diagram [see datasheet] exemplifies the flexibility of the
82C895/82C602 GREEN strategy. System designs can easily accommodate
both SLe and non-SLe CPUs. If an Intel non-SLe CPU is used, SMI#,
SMIACT#, and FLUSH# are no connects. One design can easily accomm-
odate both types of processors with minimal changes for upgrades.
***Configurations:...
***Features:...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
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