[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82370 Integrated System Peripheral (for 82376) c:Oct88
***Notes:...
***Info:
The 82370 is a multi-function support peripheral that integrates
system functions necessary in an 80376 environment. It has eight
channels of high performance 32-bit DMA (32-bit internal, 16-bit
external) with the most efficient transfer rates possible on the 80376
bus. System support peripherals integrated into the 82370 provide
Interrupt Control, Timers, Wait State generation, DRAM Refresh
Control, and System Reset logic.
The 82370's DMA Controller can transfer data between devices of
different data path widths using a single channel. Each DMA channel
operates independently in any of several modes; Each channel has a
temporary data storage register for handling non-aligned data without
the need for external alignment logic.
1.0 FUNCTIONAL OVERVIEW
The 82370 contains several independent functional modules. The
following is a brief discussion of the components and features of the
82370. Each module has a corresponding detailed section later in this
data sheet. Those sections should be referred to for design and
programming information.
1.1 82370 Architecture
The 82370 is comprised of several computer system functions that are
normally found in separate LSI and VLSI components. These include: a
high-performance, eight-channel, 32-bit Direct Memory Access
Controller; a 20-level Programmable Interrupt Controller which is a
superset of the 82C5SA; four 16-bit Programmable Interval Timers which
are functionally equivalent to the 82C54 timers; DRAM Refresh
Controller; a Programmable Wait State Generator; and system reset
logic. The interface to the 82370 is optimized for high-performance
operation with the 80376 microprocessor.
The 82370 operates directly on the 80376 bus. In the Slave Mode, it
monitors the state of the processor at all times and acts or idles
according to the commands of the host. It monitors the address
pipeline status and generates the programmed number of wait states for
the device being accessed. The 82370 also has logic to the reset of
the 80376 via hardware or software reset requests and processor
shutdown status.
After a system reset, the 82370 is in the Slave Mode. It appears to
the system as an I/O device. It becomes a bus master when it is
performing DMA transfers.
To maintain compatibility with existing software, the registers within
the 82370 are accessed as bytes. If the internal logic of the 82370
requires a delay before another access by the processor, wait states
are automatically inserted into the access cycle. This allows the
programmer to write initialization routines, etc. without regard to
hardware recovery times.
***Versions:...
***Features:...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HT44 Secondary Cache c:Jun92
***Info:
The HT44 is a look-aside write-through, 80486SX, 486DX or 486DX2
secondary cache controller. It is packaged in an inexpensive 84-pin
plastic-leaded chip carrier (PLCC).
Architecture
With its look-aside architecture, the HT44 fits beside the CPU-to-
Memory bus and not in the data path. Therefore, once the HT44 has
been designed into a 486 system, it can be populated for secondary
cache systems or left vacant for non-secondary cache systems. The HT44
is direct-mapped to the available address space.
Performance
The HT44 has a number of performance enhancing features. These
include zero-waitstate burst line fills to the 486 on secondary cache
hits, and simultaneous 486 and secondary cache updates on read misses.
Memory Configurations
The HT44 supports cache sizes from 32KBytes to 1MB. Both synchronous
and asynchronous SRAMs are supported. 25ns SRAMs are sufficient for
zero-wait-state operation at 33MHz.
Chip Set Support
The HT44 can, be implemented with minimal glue logic in a 486 system
with the HTK340 (code name Shasta) chip set. The registers in the
HTK340 allow for programming of non-cacheable and write-protected
areas of memory. The HTK340 will support the HT44 with synchronous
SRAMs only. Future Headland chip sets will support both synchronous
and asynchronous SRAM designs.
The HT44 can also be used with some third-party chip sets, however,
additional glue logic may be required.
***Versions:...
***Features:...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved