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**82360SL I/O Subsystem 10/05/90
***Notes:...
***Info:
The 82360SL Peripheral I/O contains dedicated logic to perform a
number of CPU, memory, and peripheral support functions. The 82360SL
device also contains an extensive set of programmable power management
facilities which allow minimized system energy requirements for
battery-powered portable computers.
The 82360SL includes a complete set of on-chip peripheral device
functions including two 16450 compatible serial ports, one 8-bit
Centronics interface or bi-directional parallel port, two 8254 comp-
atible timer counters, two 8259 compatible interrupt controllers, two
8237 compatible DMA controllers, one 74LS612 compatible DMA page
register, one 146818 compatible Real-time clock/calendar with an
additional 128 bytes of battery backed CMOS RAM and an integrated
drive electronics (IDE) hard disk drive interface. The Intel 82360SL
also contains highly programmable chip selects and complete peripheral
interface logic for direct keyboard and floppy disk controller
support. The peripheral registers and functions behave exactly as the
discrete components commonly found in industry standard personal
computers. The peripheral logic is enhanced for static operation by
supporting write only registers as read/write.
The processor and memory support functions contained in the 82360SL
device eliminate most of the external random-logic "glue" that might
otherwise be required. The 82360SL device provides internal
programmable-frequency clock generators for the ISA bus backplane, and
video subsystems. A programmable, low-power DRAM refresh timer is also
provided to maintain system memory integrity during the power saving
suspend state.
The 82360SL also contains a flexible set of hardware functions to
support the growing sophistication in power management schemes
required by portable systems. Numerous hardware timers, event monitors
and I/O interfaces can programmable monitor and control system
activity. Firmware developed by the system designer allocates and
directs the hardware to fulfill the unique power management needs of a
given system configuration.
All of the standard peripheral registers, clock-generation logic, and
power-management facilities have been designed to ensure complete
compatibility with existing operating systems and applications
software.
***Versions:...
***Features:...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C802G/GP System/Power Management Controller (cached) c:93
***Notes:...
***Info:
The 82C802G/GP provides a highly integrated solution for fully
compatible, high performance PC/AT platforms. This chipset will
support 486SX/DX/DX2/DX4 and P24T microprocessors in the most cost
effective and power efficient designs available today. For power
users this chipset offers optimum performance for systems running up
to 50MHz.
Based fundamentally on OPTi’s proven 82C801 and 82C802 design
architectures, the 82C802G/GP adds additional memory configurations
and extensive power management control for the processor and other
motherboard components.
The 82C802G/GP supports the latest in write-back processor designs
from Intel, AMD, and Cyrix, as well as supporting the AT bus and VESA
local bus for compatibility and performance. It also includes an
82C206 Integrated Peripherals Controller (IPC), all in a single
208-pin PQFP (Plastic Quad Plat Pack) package for low cost.
Power Management Block
Figure 2-1 [see datasheet] exemplifies the flexibility of the
82C802G/GP/82C602 GREEN strategy. System designs can easily
accommodate both SLe and non-SLe CPUs. If an Intel non-SLe CPU is
used. SMI#, SMIACT#, and FLUSH# are no connects. One design can easily
accommodate both types of processors with minimal changes for
upgrades.
***Configurations:...
***Features:...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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