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*Intel...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84
***Notes:...
***Info:
Intel's 82258, Advanced Direct Memory Access Coprocessor is a high
performance, 16 bit DMA processor optimized for the 80286, 80186 and
the 8086 families of CPUs and compatible with 80386 CPU. It has
on-chip bus interface for the whole 8086 family architecture. Four
high speed, independently programmable DMA channels can achieve a
maximum cumulative transfer rate of 8 MByte/sec in an 8 MHz 80286
system and 4 MByte/sec in 8 MHz 8086/80186 systems. Channel 3 can be
used as a Multiplexor channel, whereby, it supports 32
subchannels. This flexibility allows one to use a single DMA channel
to handle a large number of slow and medium speed I/O
devices. Advanced capabilities like Command and Data chaining and "On
the fly" operations allow the 82258 to remove the I/O management load
from the processor. The 82258 addresses the full 80286 CPU memory (16
MB for 80286), thus simplifying the system design. Automatic
assembly/disassembly of data allows 16 bit processors to interface
with common 8 bit peripherals and vice-versa. Remote mode of
operation, where the 82258 has its own resident bus, allows modular
system design. The 82258 complements the high performance,
multitasking capabilities of the 80286.
***Versions...
***Features:...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HTK340 "Shasta" 486 Chip Set c:Jun92
***Notes:...
***Info:
The HTK340 chip set is a two chip, high performance, cost-effective
solution for the 80486SX DX, and DX2 processing environments. In its
minimum configuration, this highly integrated chip set requires only
four external TTL devices to implement a fully compatible IBM PC/AT
system at speeds up to 33MHZ.
The HTK340 is based upon Headland's HTK320 Bus Architecture and
consists of the HT321-ISA Bus Controller and the HT342-Memory Control
Unit (MCU). Both chips are packaged in 184 pin plastic quad flat
packs.
The HTK340 is unique in that it provides performance approximating
that of large secondary cache systems, including the highest
performance write back cache architectures, without any external
cache. Secondary cache solutions should be considered in applications
that make use of multi-tasking and large model operating systems. The
Headland HT44 secondary cache was designed to meet the cost and
performance objectives for these applications. The key to this level
of performance is the 4-level deep write buffer, which includes byte
gathering for up to 32-bit DRAM writes.
Due to the effectiveness of the primary cache internal to the 80486
most of the bus activity in a PC/AT compatible environment consists of
writes. Indeed, this write activity consists almost exclusively of
writes of either bytes or Words (16 bit entities). In addition, much
of this write activity is into sequential memory locations. The byte
gathering feature of the buffer has the effect of reducing the number
of memory accesses required. Since the 80486 can always write into the
buffer with zero wait states (assuming the buffer is not full), and
the buffer can empty faster than it can be filled for most write
activity, the net effect is that the writes from the CPU never cause a
wait state.
The HTK340 can support Peripheral Devices such as VGA or SCSI on the
local processor bus, or any other devices that are designed to work
within the 80486 bus protocol and timing. By eliminating the ISA
backplane bottleneck, system designers can greatly improve the
performance of functions such as graphics generation and disk access.
The HTK340 supports up to 4 banks of DRAM, configurable as 1-4
banks. This flexible memory architecture allows for any memory type,
from 256K to 16M devices, in any bank. Maximum system performance is
achieved from the DRAM banks through various means, including
interleaving of memory banks and/or paging, and CAS before RAS
refresh. The memory can also be tuned to maximum potential through the
use of extensive DRAM timing control registers. These controls
include: precharge time, access time on reads, active time on writes,
as well as CAS and RAS delays. In addition, further system perfor-
mance is gained by separate timing parameters on the read and write
cycles which allow system designers to take maximum advantage of the
pipelined structure of the chip set.
The HTK340 also supports extensive mapping registers, which allow
system designers to take maximum advantage of system memory. The chip
set supports Shadow/Remap in 16K blocks between the 640K and 1M
boundaries, and eliminates the requirement for external decoding logic
by supporting 26 programmable non-cache regions. Devices which meet
HTK340 local bus requirements may be implemented without external
TTL. The mapping structure of the HTK340 provides for a single 8-bit
EPROM to be used for both the System and Video BIOS, further reducing
system chip count and cost.
***Configurations:...
***Features:...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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