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*Intel...
**82258       Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84
***Notes:...
***Info:
Intel's  82258, Advanced Direct  Memory Access  Coprocessor is  a high
performance, 16 bit  DMA processor optimized for the  80286, 80186 and
the  8086 families  of  CPUs and  compatible  with 80386  CPU. It  has
on-chip  bus interface for  the whole  8086 family  architecture. Four
high  speed, independently  programmable  DMA channels  can achieve  a
maximum  cumulative transfer rate  of 8  MByte/sec in  an 8  MHz 80286
system and 4  MByte/sec in 8 MHz 8086/80186 systems.  Channel 3 can be
used   as   a   Multiplexor   channel,   whereby,   it   supports   32
subchannels. This flexibility  allows one to use a  single DMA channel
to   handle  a   large   number   of  slow   and   medium  speed   I/O
devices. Advanced capabilities like  Command and Data chaining and "On
the fly" operations allow the  82258 to remove the I/O management load
from the processor. The 82258  addresses the full 80286 CPU memory (16
MB  for   80286),  thus  simplifying  the   system  design.  Automatic
assembly/disassembly  of data  allows 16  bit processors  to interface
with  common  8  bit   peripherals  and  vice-versa.  Remote  mode  of
operation, where  the 82258 has  its own resident bus,  allows modular
system   design.   The  82258   complements   the  high   performance,
multitasking capabilities of the 80286.

***Versions...
***Features:...
**82335       High-Integration Interface Device For 386SX      c:Nov88...
**82360SL     I/O Subsystem                                   10/05/90...
**82370       Integrated System Peripheral (for 82376)         c:Oct88...
**82371FB/SB  PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX     Mobile PCI I/O IDE Xcelerator (MPIIX)           11/01/95...
**82371AB     PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4)     02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB)   c:Mar93...
**82378       System I/O (SIO) (82378IB and 82378ZB)           c:Mar93...
**82379AB     System I/O-APIC (SIO.A)                           <Dec94...
**82380       32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB  PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384       Clock Generator and Reset Interface                  c86...
**82385       32-bit Cache Controller for 80386               09/29/87...
**82385SX     32-bit Cache Controller for 80386SX             01/25/89...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor  to form a CPU Cache chip  set designed for high
performance  servers  and   function-rich  desktops.  The  high  speed
interconnect between  the CPU and cache components  has been optimized
to  provide zero-wait  state operation.   This CPU  Cache chip  set is
fully compatible  with existing software,  and has new  data integrity
features for mission critical applications.

The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82496  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit  wide memory bus widths,  16, 32, and 64  byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82491, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92
***Notes:...
***Info:...
***Configurations:...
***Features:...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
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