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**8289 Bus Arbiter (808x) c79
***Notes:...
***Info:
The Intel 8289 Bus Arbiter is a 20-pin, 5-volt-only bipolar component
for use with medium to large iAPX 86, 88 multimaster/multiprocessing
systems. The 8289 provides system bus arbitration for systems with
multiple bus masters, such as an 8086 CPU with 8089 IOP in its REMOTE
mode, while providing bipolar buffering and drive capability.
FUNCTIONAL DESCRIPTION
The 8289 Bus Arbiter operates in conjunction with the 8288 Bus
Controller to interface iAPX 86, 88 processors to a multi-master
system bus (both the iAPX 86 and iAPX 88 are configured in their max
mode). The processor is unaware of the arbiter's existence and issues
commands as though it has exclusive use of the system bus. If the
processor does not have the use of the multi-master system bus, the
arbiter prevents the Bus Controller (8288), the data transceivers and
the address latches from accessing the system bus (e.g. all bus driver
outputs are forced into the high impedance state). Since the command
sequence was not issued by the 8288, the system bus will appear as
"Not Ready" and the processor will enter wait states. The processor
will remain in Wait until the Bus Arbiter acquires the use of the
multi-master system bus whereupon the arbiter will allow the bus
controller, the data transceivers, and the address latches to access
the system. Typically, once the command has been issued and a data
transfer has taken place, a transfer acknowledge (XACK) is returned to
the processor to indicate" READY" from the accessed slave device. The
processor then completes its transfer cycle. Thus the arbiter serves
to multiplex a processor (or bus master) onto a multi-master system
bus and avoid contention problems between bus masters.
***Versions:...
***Features:...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HT44 Secondary Cache c:Jun92
***Info:
The HT44 is a look-aside write-through, 80486SX, 486DX or 486DX2
secondary cache controller. It is packaged in an inexpensive 84-pin
plastic-leaded chip carrier (PLCC).
Architecture
With its look-aside architecture, the HT44 fits beside the CPU-to-
Memory bus and not in the data path. Therefore, once the HT44 has
been designed into a 486 system, it can be populated for secondary
cache systems or left vacant for non-secondary cache systems. The HT44
is direct-mapped to the available address space.
Performance
The HT44 has a number of performance enhancing features. These
include zero-waitstate burst line fills to the 486 on secondary cache
hits, and simultaneous 486 and secondary cache updates on read misses.
Memory Configurations
The HT44 supports cache sizes from 32KBytes to 1MB. Both synchronous
and asynchronous SRAMs are supported. 25ns SRAMs are sufficient for
zero-wait-state operation at 33MHz.
Chip Set Support
The HT44 can, be implemented with minimal glue logic in a 486 system
with the HTK340 (code name Shasta) chip set. The registers in the
HTK340 allow for programming of non-cacheable and write-protected
areas of memory. The HTK340 will support the HT44 with synchronous
SRAMs only. Future Headland chip sets will support both synchronous
and asynchronous SRAM designs.
The HT44 can also be used with some third-party chip sets, however,
additional glue logic may be required.
***Versions:...
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