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**82091AA     Advanced Interface Peripheral (AIP)                  c93
***Notes:...
***Info:...
***Versions:...
***Features:
o   Single-Chip PC Compatible I/O Solution for Notebook and Desktop 
    Platforms:
    - 82078 Floppy Disk Controller Core
    - Two 16550 Compatible UARTs
    - One Multi-Function Parallel Port
    - IDE Interface
    - Integrated Back Power Protection
    - Integrated Game Port Chip Select
    - 5V or 3.3V Supply Operation with 5V Tolerant Drive Interface
    - Full Power Management Support
    - Supports Type F DMA Transfers for Faster I/O Performance
    - No Wait-State Host I/O Interface
    - Programmable Interrupt Interfaces
    - Single Crystal/Oscillator Clock (24 MHz)
    - Software Detectable Device ID
    - Comprehensive Powerup Configuration
o   The AIP is 100 Percent Compatible with EISA, ISA and AT
o   Host Interface Features
    - 8-Bit Zero Wait-State ISA Bus Interface
    - DMA with Type F Transfers
    - Five Programmable ISA Interrupt Lines
    - Internal Address Decoder
o   Parallel Port Features
    - All IEEE Standard 1284 Protocols Supported (Compatibility, 
      Nibble, Byte, EPP, and ECP)
    - Peak Bi-Directional Transfer Rate of 2 MB/sec
    - 16-Byte FIFO for ECP
o   Floppy Disk Controller Features
    - 100% Software Compatible with Industry Standard 82077SL and
    - Integrated Analog Data Separator 250K, 300K, 500K, and 1M
    - Programmable Powerdown Command
    - Auto Powerdown and Wakeup Modes
    - Integrated Tape Drive Support
    - Perpendicular Recording Support for 4 MB Drives
    - Programmable Write Pre-Compensation Delays
    - 256 Track Direct Address, Unlimited Track Support
    - 16-Byte FIFO
    - Supports 2 or 4 Drives
o   16550 Compatible UART Features
    - Two Independent Serial Ports
    - Software Compatible with 8250 and 16450 UARTs
    - 16-Byte FIFO per Serial Port
    - Two UART Clock Sources, Supports MIDI Baud Rate
o   IDE Interface Features
    - Generates Chip Selects for IDE Drives
    - Integrated Buffer Control Logic
    - Dual IDE Interface Support
o   Power Management Features
    - Transparent to Operating Systems and Applications Programs
    - Independent Power Control for Each Integrated Device
o   100-Pin QFP Package


**8289        Bus Arbiter (808x)                                   c79...
**82289       Bus Arbiter for iAPX 286 Processor Family            c83...
**82258       Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335       High-Integration Interface Device For 386SX      c:Nov88...
**82360SL     I/O Subsystem                                   10/05/90...
**82370       Integrated System Peripheral (for 82376)         c:Oct88...
**82371FB/SB  PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX     Mobile PCI I/O IDE Xcelerator (MPIIX)           11/01/95...
**82371AB     PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4)     02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB)   c:Mar93...
**82378       System I/O (SIO) (82378IB and 82378ZB)           c:Mar93...
**82379AB     System I/O-APIC (SIO.A)                           <Dec94...
**82380       32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB  PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384       Clock Generator and Reset Interface                  c86...
**82385       32-bit Cache Controller for 80386               09/29/87...
**82385SX     32-bit Cache Controller for 80386SX             01/25/89...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:
The Intel 82495XP cache controller and 82490XP cache RAM, when coupled
with a user-implemented memory  bus controller, provide a second-level
cache  subsystem  that eliminates  the  memory  latency and  bandwidth
bottleneck for  a wide  range of multiprocessor  systems based  on the
i860 XP  microprocessor. The CPU  interface is optimized to  serve the
i860  XP microprocessor  with zero  wait  states at  up to  50 MHz.  A
secondary cache  built from the  82495XP and 82490XP isolates  the CPU
from  the memory subsystem;  the memory  can run  slower and  follow a
different protocol than the i860 XP microprocessor.
         
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
**SL9250  Page Mode Memory Controller (16/20MHz 8MB Max)        <oct88
***Info:...
***Versions:...
***Features:...
**SL9350  Page Mode Memory Controller (16/20/25MHz 16MB Max)    <oct88...
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