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**82430HX PCIset (Pentium) HX (Triton II) (82439HX) 02/12/96
***Notes:...
***Info:...
***Configurations:...
***Features:
o Supports All 3V Pentium Processors
o Dual Processor Support
o PCI 2.1 Compliant
o Integrated Second-Level Cache Controller
- Direct Mapped Organization
- Write-Back Cache Policy
- Cacheless, 256 KB, and 512 KB
- Pipelined Burst SRAMs
- Cache Hit Read/Write Cycle Timings at 3-1-1-1
- Back-to-Back Read Cycles at 3-1-1-1-1-1-1-1
- Integrated Tag/Valid Status Bits for Cost Savings and
Performance
- Optional 512-MB DRAM Cacheability Limit
- Supports 5V SRAMs for Tag Address
o Integrated DRAM controller
- 4-MB to 512-MB Main Memory
- 64-Mb DRAM Technology Support
- 8-QWord Deep Merging DRAM Write Buffer
- Enhanced EDO/Hyper Page Mode DRAM; 4-2-2-2 Beads and x-2-2-2
Writes at 60 MHz; 5-2-2-2 Reads and x-2-2-2 Writes at 66 MHz
- 8 RAS Lines
- Integrated Programmable-Strength Memory Address Butters
- CAS-Before-RAS Refresh
o Optional Parity
o Single 324-Pin BGA Package
o Optional Error Checking and Correction (ECC)
- Superior DRAM Data integrity
- Single Bit Error Correction, Multi-Bit Error Detection plus
Nibble
Failure Detection ECC Code
- Single and Multi-Bit Error Reporting
- Virtual Swapable Bank Support (i.e., can swap out problem banks)
- Merging Write Buffer Eliminates Most Partial Writes Cycles
o Fully Synchronous, Minimum Latency 25/30/33 MHz PCI Bus interface
- Zero Wait State CPU-to-PCI Write Timings (no IRDY stall) for
Superior Graphics Performance
- Enhanced CPU-to-PCI Read Latencies for Superior Graphics/PIO
Performance
- 21-DWord PCI-DRAM Post Buffer
- 22-DWord PCI-to-DRAM Read Prefetch Buffer
- Write-Back Merging for PCI to DRAM Writes
- Write-Back Forwarding for PCI to DRAM Reads
- Pipelined Snoop Ahead
- Multi-Transaction Timer to Support
- Multiple Short PCI Transactions Within the Same PCI Arbitration
Cycle
o Supports the Universal Serial Bus (USB)
o Supported Kits
- 82439HX ISA Kit (Txc, PIIX3)
- 82439HX ISA/DP Kit (TXC, PIIX3, IOAPIC)
**82430VX PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96...
**82430TX PCIset (Pentium) TX (Triton II) (82439TX) 02/17/97...
**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
**8289 Bus Arbiter (808x) c79...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93
***Notes::...
***Info:
The OPTi design team is proud to present the 64-bit Pentium AT
solution with VESA Local bus. As always, the product emphasis is on
value. The OPTi PTMAWB is crafted to provide the highest performance
but most cost effective system solution without compromising quality,
compatibility or reliability.
The PTMAWB is a top-of-the-line solution for the server/power user
market. Flexibility of design without using the most expensive support
parts has been given key importance. This ensures the total system
cost to be at the high-end 486 level - yet with the high-end Pentium
performance.
The PTMAWB has the state-of-the-art AWB cache controller for up to 2
MB of Adaptive Write-back cache support. The DRAM controller also
supports posted writes for faster performance on write cycles.
The OPTi PTMAWB-V provides PC servers and PC power users the
horsepower of the 64-bit Pentium at 60 MHz and 66 MHz-immediately.
***Configurations:...
***Features:...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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