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**Definition of a chip set:
In short it is a set of chips that allow a system designer to build a
computer. If we restrict the term 'chip' to that of a microchip then
technically any microcomputer contains a chip set, even one based of
7400-series logic alone.
In the context of this document, a chip set is defined as any group of
chips used to implement an IBM or IBM-compatible PC/XT/AT/386/486/etc
system.
There are 2 main categories that these chips fall into:
1. Direct copies or re-implementations of Intel chips
2. Chip sets sold as a set of chips to implement an IBM-compatible
that differ in some way to those used in an IBM system, e.g. not
pin compatible.
An example of the former would be some early chips built by VLSI
Technology (at the time known as VTI, to implement a 286:
o VL82C37A is a: 82C37A DMA controller
o VL82C59A is a: 82C59A interrupt controller
o VL82C54A is a: 82C54 timer
o VL82C612 is a: 74LS612 memory mapper
o VL82C84A is a: 82284 clock generator and ready interface
o VL82C88 is a: 82288 bus controller
These are all direct replacements for the parts used in an IBM AT.
Many companies had compatible versions of these chips.
An early example of the latter is the Chips & Technology NEAT chip set:
o 82C211 CPU/Bus controller,
o 82C212 Page/Interleave and EMS Memory controller,
o 82C215 Data/Address buffer
o 82C206 Integrated Peripherals Controller (IPC).
The description does not map directly to the parts used in the IBM AT.
Later chip sets are often even more integrated sometimes consisting of
just one chip, although two seems to be the most common.
The latter is generally considered the definition of a chip set, and
the former is not generally considered a chip set per-se. However when
looking at the early chip sets this distinction can be very
slight. Because of this, sets of chips meeting the criteria for (1.)
have been included where possible.
**'chip set', 'chip-set' or 'chipset'?...
**What's not included:...
**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**440 series:
***440FX (Natoma) 05/06/96...
***440LX (Balboa) 08/27/97...
***440BX (Seattle) c:Apr'98...
***440DX (?) c:?...
***440EX (?) c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99
Chips:
[82443ZX] (PAC) [82371EB] (PIIX4E)
CPUs: Single P-II/Celeron
DRAM Types: EDO SDRAM
Mem Rows: 4
DRAM Density: 16Mbit 64Mbit
Max Mem: 256MB
ECC/Parity: No
AGP speed: 1x 2x
Bus Speed: 66 100 133*1
PCI Clock/Bus: 1/2 1/3 1/4*1 PCI 2.1
440ZX-66 is the same but only has bus speed of 66 MHz and PCI divisor
or 1/2.
>*1 Exists but unofficially. There is no 1/2 divider for AGP,
making AGP unstable in a 133MHz bus system. In this config. the
system is overclocked.
***440ZX-M (?) 05/17/99...
***440MX (Banister) 05/17/99...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
**SL82C470 'Mozart' 486/386 EISA chipset c:Dec91
***Info:
The SL82C470 chip set provides a very high performance. highly inte-
grated and cost-effective implementation for personal computer systems
based on the standard EISA bus. It supports both 386DX and 486DX/SX
CPUs over the entire performance range, from 20Mhz to 50Mhz. The chip
set can operate in either "conventional" or "concurrent" config-
uration. Under the conventional configuration, the cache subsystem is
dedicated to bus snooping when a DMA or master device becomes active.
Under the concurrent configuration, the CPU-cache operation continues
while bus snooping is performed for the DMA or master device to
explore maximum concurrency between the CPU and the EISA bus. Only
ten TTLs are required for a complete motherboard design under the
conventional configuration in addition to the chip set and memory
devices. Five additional TTLs are required for the concurrent
configuration. A complete EISA system of either configuration can be
easily implemented on a baby AT sized motherboard.
The SL82C470 chip set consists of three 160-pin PQFP devices: the
SL82C471 integrated cache/DRAM controller, the SL82C472 EISA bus
controller and the SL82C473 DMA controller.
SL820471 Cache/DRAM Controller
The SL82C47l Cache/DRAM controller controls the cache and DRAM
accesses from the CPU, EISA/ISA masters and DMA devices. The chip
adapts a write-back cache scheme to minimize the interference between
the CPU-cache and DMA/master during their concurrent operations. The
cache size ranges from 64KB to 1MB with advanced features such as
2-1-1-1 burst line fill. Snoop-filtering, local bus support and
programmable non-cacheable and write-protected regions. The page mode
DRAM controller supports 1 to 4 banks of DRAMS up to 256MB. A mixture
of 256KB, 1MB. 4MB and 16MB DRAMs is supported. The video and system
BIOS can be shadowed or cached independently. The cache-DRAM
subsystem allows zero wait state burst mode DMA transfers to take full
advantage of the high bandwidth of the EISA bus.
The DRAM data bus can either be connected directly to the CPU local
bus or be buffered externally, The control signals for the external
buffers are generated by the SL82C471.
SL82C472 EISA Bus Controller
The SL82C472 EISA bus controller translates bus control signals
between the CPU, EISA/ISA and DMA masters and slaves. The chip also
includes buffers and byte/word swap logic between the CPU (or DRAM)
and the EISA bus. The bus conversion and data alignment are performed
automatically.
The SL82C472 includes two 8259 interrupt controllers and four 8254
timer channels modified for 100% EISA compatibility. The chip also
includes parity generation and check logic and NMI and timeout logic.
SL82C473 EISA DMA Controller
The SL82C473 DMA controller implements seven EISA DMA channels. the
system arbiter and the co-processor interface logic. The DMA control-
ler supports compatible type A, type B and type C (burst) mode
operations with the buffer chaining capability. The multilevel
rotating priority arbitration with fail-safe timeout is implemented
for the system arbiter. Six sets of slot-specific master handshake
signals (MACK and MREQ) are provided directly without any external
components.
The address latches and buffers for the EISA bus are also included in
the SL82C473.
***Configurations:...
***Features:...
**SL82C490 'Wagner' 486? [no datasheet] ?...
**SL82C550 'Rossini' Pentium [no datasheet] c:95...
**
**Support Chips:
**SL82C365 Cache Controller (for 386DX/SX) c:91...
**SL82C465 Cache Controller (for 486/386DX/SX) c:91...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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