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**82340SX Chip Set (VLSI) (82343/82344) 01/25/89
***Notes:...
***Info:...
***Configurations:...
***Features:
o Two Chip ISA (Industry Standard Architecture) Chip Set Capable
of Use in 386 SX-Based Systems Up to 20 MHz
o Both Chips are 160 Quad Flatpacks 1.0- and 1.5-Micron CMOS
o Memory Control of One to Four Banks of 16-Bit DRAM Using 256K,
1M, or 4M Components Allowing 32 Mbytes on System Board
o Page Mode DRAM Operation on Any Number of Banks
o Two/Four-way Interleaving or Direct Access on System Board
Memory
o Programmable Option for block or Word Interleave
o Programmable DRAM Timing Parameters
o Remap Option Allows Logical Reordering of System Board DRAM
o System Board Refresh Optionally Decoupled from Slot Bus
Refresh
o Staggered Refresh Minimizes Power Supply Load Variations
o Built-in "Sleep" Mode Features Including Use of Slow Refresh
DRAMs in Power Critical Operations
o EMS Hardware Supports Full LIM EMS 4.0 Spec over Entire 32 Mbyte
Memory Map with Backfill to 256K-Includes Tow Sets of 36 Mapping
Registers Each
o Shadow RAM Support in 16K increments over Entire 640K to 1M range
o Support for 387SX Numerical Coprocessors
o Software Coprocessor Reset can be Disabled
o Internal Switching and Programmable CLK2 Support for Slow and
"Turbo" Modes
o Programmable Drive on DRAM and Slot Bus Interface Signals Allows
Direct Tailored to System Size
o Asynchronous or Synchronous Slot Bus Operation with Programmable
bus Clock Divider
o Bus "Quiet" Mode Assures that Slot Bus Signal Lines are Driven Only
During Slot Accesses
o Integrated Peripheral Functions:
- Two 82C37A DMA Controllers
- Two 82C59A Interrupt Controllers
- One 82C54 Timer
- One 148618 Real Time Clock
o Supports 8- or 16-Bit Wide BIOS ROMs
o I/O Decode Programmable for 10- or 16-Bit Addresses
o Separate Parity Generators/Checkers for High Speed Operation
o Designed for Systems with Up to 12 MHz Backplane Operation
o Three-State Control Pins Added for Board Level Testability
o Compatible with Lotus 1-2-3 Version 3.0 in 1M Systems
**82350 EISA Chip Set 07/10/89...
**82350DT EISA Chip Set 04/22/91...
**82420TX/ZX PCIset (for 486) TX (Saturn), ZX (Saturn II) c:Nov92...
**82420EX PCIset (for 486) EX (Aries) (82425EX/82426EX) <Dec94...
**82430LX PCIset (Pentium) LX (Mercury) (82433LX/82434LX) 03/22/93...
**82430NX PCIset (Pentium) NX (Neptune) (82433NX/82434NX) Mar94...
**82430FX PCIset (Pentium) FX (Triton I) (82437FX/82438FX)01/31/95...
**82430MX PCIset (Pentium) MX (Mobile Triton)(82437/438MX)11/01/95...
**82430HX PCIset (Pentium) HX (Triton II) (82439HX) 02/12/96...
**82430VX PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96...
**82430TX PCIset (Pentium) TX (Triton II) (82439TX) 02/17/97...
**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
**8289 Bus Arbiter (808x) c79...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HT44 Secondary Cache c:Jun92
***Info:
The HT44 is a look-aside write-through, 80486SX, 486DX or 486DX2
secondary cache controller. It is packaged in an inexpensive 84-pin
plastic-leaded chip carrier (PLCC).
Architecture
With its look-aside architecture, the HT44 fits beside the CPU-to-
Memory bus and not in the data path. Therefore, once the HT44 has
been designed into a 486 system, it can be populated for secondary
cache systems or left vacant for non-secondary cache systems. The HT44
is direct-mapped to the available address space.
Performance
The HT44 has a number of performance enhancing features. These
include zero-waitstate burst line fills to the 486 on secondary cache
hits, and simultaneous 486 and secondary cache updates on read misses.
Memory Configurations
The HT44 supports cache sizes from 32KBytes to 1MB. Both synchronous
and asynchronous SRAMs are supported. 25ns SRAMs are sufficient for
zero-wait-state operation at 33MHz.
Chip Set Support
The HT44 can, be implemented with minimal glue logic in a 486 system
with the HTK340 (code name Shasta) chip set. The registers in the
HTK340 allow for programming of non-cacheable and write-protected
areas of memory. The HTK340 will support the HT44 with synchronous
SRAMs only. Future Headland chip sets will support both synchronous
and asynchronous SRAM designs.
The HT44 can also be used with some third-party chip sets, however,
additional glue logic may be required.
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