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*ACC Micro...
**ACC2051/NT PCI Single Chip Solution for Notebook Applications c96
***Info:...
***Configurations:
Versions:
2051NT
2051
According to this site:
http://www.idhw.com/textual/chip/acc/chipname.html
The 2051 is the same as the 2051NT, sans IDE.
***Features:...
**ACC2056 ?Pentium 3.3V Notebook [no datasheet]<Jan96...
**ACC2057 PCI Notebook/Embedded Single Chip [no datasheet]<Aug96...
**ACC2066NT 486 Notebook/Embedded Single Chip [no datasheet] ?...
**ACC2086 486 VL-based System Super Chip Soluti[no datasheet] ?...
**ACC2087 Enhanced Super Chip (486 Single Chip) <Aug96...
**ACC2089 486 PCI-based System Super Chip [no datasheet] ?...
**ACC2168/GT 32-bit 486 Green System Single Chip [no datasheet] ?...
**ACC2178A 32-bit 486 Green System Single Chip [no datasheet] ?...
**ACC2268 ?486 [no datasheet] ?...
**ACC???? Maple/Maple-133 486-System-On-Chip [no datasheet] ?...
**
**Support Chips:
**ACC2016 Buffer and MUX Logic c96...
**ACC2020 Power Management Chip c92...
**ACC5500 Multifunction I/O Control Chip for PS2 Model 50/60 c88...
**
**Other chips...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:
o High Performance Second Level Cache
- Zero Walt States at 66 MHz
- Two-way Set Associative
- Write-Back with MESI Protocol
- Concurrent CPU Bus and Memory Bus Operation
- Boundary Scan
o Pentium Processor
- Chip Set Version of Pentium Processor
- Superscalar Architecture
- Enhanced Floating Point
- On-chip SK Code and SK Data Caches
- See Pentium Processor User's Manual Volume 2 for more
Information
o Highly Flexible
- 256K to 512K with parity
- 32, 64, or 128-Bit Wide Memory Bus
- Synchronous, Asynchronous, and Strobed Memory Bus Operation
- Selectable Bus Widths, Line Sizes, Transfers, and Burst Orders
o Full Multiprocessing Support
- Concurrent CPU, Memory Bus, and Snoop Operations
- Complete MESI Protocol
- Internal/External Parity Generation/Checking
- Supports Read-for Ownership, Write-Allocation, and Cache-to-
Cache Transfers
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*TI (Texas Instruments)...
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*Unresearched:...
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*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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