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*ACC Micro...
**ACC2036 Single Chip Solution 2036 (286/386SX) <Jul92
***Info:...
***Configurations:...
***Features:...
**ACC2046/ST 486DX/486SX/386DX Single Chip AT <Jul92...
**ACC2048 WB 486 Notebook/Embedded Single Chip [no datasheet] ?...
**ACC2051/NT PCI Single Chip Solution for Notebook Applications c96...
**ACC2056 ?Pentium 3.3V Notebook [no datasheet]<Jan96...
**ACC2057 PCI Notebook/Embedded Single Chip [no datasheet]<Aug96...
**ACC2066NT 486 Notebook/Embedded Single Chip [no datasheet] ?...
**ACC2086 486 VL-based System Super Chip Soluti[no datasheet] ?...
**ACC2087 Enhanced Super Chip (486 Single Chip) <Aug96...
**ACC2089 486 PCI-based System Super Chip [no datasheet] ?...
**ACC2168/GT 32-bit 486 Green System Single Chip [no datasheet] ?...
**ACC2178A 32-bit 486 Green System Single Chip [no datasheet] ?...
**ACC2268 ?486 [no datasheet] ?...
**ACC???? Maple/Maple-133 486-System-On-Chip [no datasheet] ?...
**
**Support Chips:
**ACC2016 Buffer and MUX Logic c96...
**ACC2020 Power Management Chip c92...
**ACC5500 Multifunction I/O Control Chip for PS2 Model 50/60 c88...
**
**Other chips...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C895 System/Power Management Controller (cached) c:Sep94
***Notes:...
***Info:
Overview
The 82C895 provides a highly integrated solution for fully compatible,
high performance PC/AT platforms. This chipset will support 486SX/
DX/DX2/DX4 and P24T microprocessors in the most cost effective and
power efficient designs available today. For power users, this
chipset offers optimum performance for systems running up to 50MHz.
Based fundamentally on OPTi's proven 82C801 and 82C802 design
architectures, the 82C895 adds additional memory configurations and
extensive power management control for the processor and other
motherboard components.
The 820895 supports the latest write-back processor designs from
Intel, AMD, and Cyrix, as well as supporting the AT bus and VESA local
bus for compatibility and performance. It also includes an
82C206-compatible Integrated Peripherals Controller (IPC). all in a
single 208-pin PQFP (Plastic Quad Flat Pack) package for low cost.
2.1 Power Management
This block diagram [see datasheet] exemplifies the flexibility of the
82C895/82C602 GREEN strategy. System designs can easily accommodate
both SLe and non-SLe CPUs. If an Intel non-SLe CPU is used, SMI#,
SMIACT#, and FLUSH# are no connects. One design can easily accomm-
odate both types of processors with minimal changes for upgrades.
***Configurations:...
***Features:
o Processor interface:
- Intel 80486SX, DX, DX2, SLe, DX4, P24T, P24D
- AMD 486DX, DX2, DXL, DXL2, Plus
- Cyrix DX, DX2, M7
- CPU frequencies supported 20, 25, 33, 40 and 50MHz
o Cache interface:
- Direct Mapped Cache
- Two banks interleaved or single bank non-interleaved
- 64, 128, 256 and 512K cache sizes
- Programmable wait states for L2 cache reads and writes
- 2-1-1-1 read burst and zero wait state write @ 33MHz
- No Valid bit required
- Supports CPUs with L1 write-back support
o DRAM interface:
- Up to 128MB main memory support
- Supports 256KB, 1MB, 4MB, and 16MB single- and double-sided SIMM
modules
- Read page-hit timing of 3-2-2-2 at 33MHz
- Supports hidden, slow and CAS-before-RAS refresh
- Four RAS lines to support four banks of DRAM
- Programmable wait states for DRAM reads and writes
- Enhanced DRAM configuration map
o Power management:
- Support for SMM (System Management Mode) for system power
management implementations
- Programmable power management
- Programmable wake-up events through hardware, software and
external SMI source
- Multiple level GREEN support (NESTED_GREEN)
- STPCLK# protocol support
- One programmable GREEN event timer
o ISA interface:
- 100% IBM PC/AT ISA compatible
- Integrates DMA, timer and interrupt controllers
- Optional PS/2 style IRQ1 and 12 latching
o VESA VL interface:
- Conforms to the VESA v2.0 specification
- Optional support for up to two VL masters
o Miscellaneous features:
- Full support for shadow RAM, write protection, L1/L2
cacheability for video, adapter and system BIOS
- Enhanced arbitration scheme
- Transparent 8042 emulation for fast CPU reset and GATEA20
generation
o Packaging:
- Higher integration
- Reduced TTL count
- Low-power, high-speed 0.8-micron CMOS technology
- 208-pin PQFP (Plastic Quad Flat Pack)
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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