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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:
o   High Performance Second Level Cache
    - Zero Wait States at 66 MHz 
    - Two-Way Set Associative 
    - Writeback with MESI Protocol 
    - Concurrent CPU Bus and Memory Bus Operation 
    - Boundary Scan
o   Pentium Processor (735\90, 815\100)
    - Chip Set Version of Pentium Processor (735\90, 815\100) 
    - Superscalar Architecture
    - Enhanced Floating Point 
    - On-Chip 8K Code and 8K Data Caches
    - See Pentium Processor Family Data Book for More Information
o   Highly Flexible
    - 1 Mbyte to 2 Mbyte
    - 64-, or 128-Bit Wide Memory Bus
    - Synchronous, Asynchronous and Strobed Memory Bus Operation
    - Selectable Bus Widths, Line Sizes, Transfers and Burst Orders
o   Full Multiprocessing Support
    - Concurrent CPU, Memory Bus and Snoop Operations
    - Complete MESI Protocol
    - Internal/External Parity Generation/Checking
    - Supports Read For Ownership, Write-Allocation and Cache-to-Cache
      Transfers


**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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**PII/III/Pro
***Notes (Unverified Information!):...
***5600        c:Nov98...
***600         ?...
***620         c:Apr99...
***621         ?...
***630/630E/S  c:Feb00...
***630ST/ET    ?
Chips:  
[630ST] or [630ET]         
CPUs:          P-III P-III(T) Celeron,               
DRAM Types:    SDRAM PC133 Asynch Mem
Max Mem:       3GB,                       
ECC/Parity:    No,           
AGP speed:     Integrated SiS301
Bus Speed:     66 100 133,          
PCI Clock/Bus: Asynch PCI 2.2


***633/633T    c:Mar01...
***635/635T    c:Mar01...
***640T        c:Mar01      ...
**Athlon etc...
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*Unresearched:...
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*General Sources:...