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**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor  (735\90, 810\100) to form a  CPU Cache chip set
designed for high performance servers and function-rich desktops.  The
high-speed interconnect between the  CPU and cache components has been
optimized to  provide zero-wait state  operation. This CPU  Cache chip
set  is fully  compatible with  existing  software, and  has new  data
integrity features for mission critical applications.

The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82497  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The  82492 is a  customized high-performance  SRAM that  supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82492, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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**FE2011        CPU Core Logic for PS/2 Model 30 Compatible       c:87
***Info:...
***Versions:...
***Features:
o   100% hardware (register level) and software compatible with IBM
    PS/2 Model 30
o   Supports 8086, 80C86 and V30 processors
o   High performance 10 MHz, zero wait state operation
o   One chip includes all CPU core logic for compatible IBM PS/2 Model 
    30 designs:
    - 8237A compatible DMA controller 
    - 8259A compatible interrupt controller with all PS/2 Model 30 
      extensions
    - 8253 compatible timer
    - 8255 compatible PIO port
    - Bus control logic
    - Clock generation logic
    - DRAM control logic
    - Address and data buffers
o   True Model 30 compatible bidirectional keyboard and mouse ports
o   Software selectable CPU clock and DMA wait state 
o   System board I/O decoder
o   Integrated EMS (LIM) support for version 4.0 EMS specification
o   Variable RAM configurations: 64K, 256K, 1M DRAM
o   Typical Model 30 CPU would consist of FE201l, 8086, 2 crystals, 
    2 TTL devices and memory
o   132-pin JEDEC Standard package
o   Low power CMOS

**FE3400/B      80286-Based AT Compatible CPU Core Logic (12 MHz) c:86...
**FE3500/B      80286-Based AT Compatible CPU Core Logic (12 MHz) c:87...
**FE3600/A/B/C  16/20MHz AT Chip set                              c:88...
**FE5300        CPU Core Logic for PS/2 Model 50/60 Compatibles   c:87...
**FE5400        CPU Core Logic for PS/2 Model 50/60 Compatibles   c:87...
**FE6500        CPU Core Logic for PS/2 Model 70/80 Compatibles   c:88...
**WD6400SX/LP   CPU Core Logic for PS/2 386SX Compatibles          <90...
**WD6500        CPU Core Logic for PS/2 386DX/486 Compatible       <90...
**WD7600A/LP/LV System Chip Set for 80286 or 80386SX         <11/25/91...
**WD7700/LP     System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD7855        System controller for 80386SX                <09/25/92...
**WD7900/LP/LV  System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD8110        System controller for 80386DX/486            <11/30/93...
**
**Support Chips:
**WD76C20x   Floppy, RTC, IDE and Support Logic Device       <11/25/91...
**WD76C30x   Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615     Desktop Buffer Manager                          <04/15/92...
**WD7625     Desktop Buffer Manager                          <10/01/92...
**WD8120LV   Super I/O [no datasheet]                                ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...