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**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor  (735\90, 810\100) to form a  CPU Cache chip set
designed for high performance servers and function-rich desktops.  The
high-speed interconnect between the  CPU and cache components has been
optimized to  provide zero-wait state  operation. This CPU  Cache chip
set  is fully  compatible with  existing  software, and  has new  data
integrity features for mission critical applications.

The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82497  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The  82492 is a  customized high-performance  SRAM that  supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82492, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**VL82C108 TOPCAT Combination I/O chip                               ?
***Info:...
***Versions:...
***Features:
o   Combines the following PC/AT compatible peripheral chips:
    VL16C450 UART         - COM!:
    Parallel Printer Port - LPT1: 
    Keyboard/Mouse Ctrl.  - KBD
o   Serial ports fully 16C450-compatible
o   Bidirectional; line printer port
o   CMOS direct drive of Centronics-type parallel interface
o   PC/AT- or PS/2-compatible keyboard and mouse controller
o   IDE bus control signals include (two external 74LS245 and one 
    74ALS244 - or equivalent - buffers are required)
o   Selectable chip select decodes
o   Resides on SD bus directly
o   Software controlled power-down with automatic keyboard "wakeup" 
    option
o   Single 100-lead plastic quad flat pack


**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
**Video: ...
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**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...