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**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor (735\90, 810\100) to form a CPU Cache chip set
designed for high performance servers and function-rich desktops. The
high-speed interconnect between the CPU and cache components has been
optimized to provide zero-wait state operation. This CPU Cache chip
set is fully compatible with existing software, and has new data
integrity features for mission critical applications.
The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual ported buffers and registers allow
the 82497 to concurrently handle CPU bus, memory bus, and internal
cache operation for maximum performance.
The 82492 is a customized high-performance SRAM that supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring. The data path between the CPU bus and memory
bus is separated by the 82492, allowing the CPU bus to handshake
synchronously, asynchronously, or with a strobed protocol, and
allowing concurrent CPU bus and memory bus operations.
***Configurations:...
***Features:...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**VL82C108 TOPCAT Combination I/O chip ?
***Info:
The VL82C108 Combo chip replaces with a single 100-pin chip, several
of the commonly used peripherals found in PC/AT-compatible
computers. This chip, when used with VLSI PC/AT-compatible chip set,
allows designers to implement a very cost-effective minimum chip count
motherboard containing functions that are common to virtually all PCs.
The on-chip UART is completely software compatible with the VL16C450
ACE.
The bidirectional parallel port provides a PS/2 software compatible
interface between a Centronics-type printer and the VL82C108. Direct
drive is provided so that all that is needed to interface to the line
printer is a resistor/ capacitor network. the bidirectional feature
(option) is software programmable for backwards PC/AT-compatibility.
The keyboard/mouse controller is selectable as PC/AT- or PS/2-
compatible.
Included is the control logic necessary for the support of the
Integrated Drive Electronics (IDE) hard disk bus interface. Hard disk
drives which support the IDE interface often refer to the interface as
"AT Bus" compatible or "Embedded AT Bus" compatible.
The Combo I/O chip also includes selectable chip selects for the
internal UART and printer port, and four fixed chip selected for
external floppy and hard disk controllers.
***Versions:...
***Features:...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
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**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
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