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**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:
Date source: 1995_Intel_Pentium_Processors_and_Related_Components.pdf

Information taken from: 
            1995_Intel_Pentium_Processors_and_Related_Components.pdf*
                                         8249x Cache controllers.pdf**
>*  Datasheet dated Nov'94
>** Datasheet undated, whole document dated '95

The info and features section have  been solely sourced from the first
source.   The  second source  provides  far  more detail.   Additional
information in the configurations section  and below have been sourced
from the second.

"Although the 82497 Cache Controller  is part of the Pentium processor
(735\90, 815\100, 1000\120, 1110\133) CPU-Cache Chip Set and the 82496
Cache  Controller is part  of the  Pentium Processor  (510\60, 567\66)
Chip  Set, the  two parts  are functionally  identical except  for the
differences noted in this section." - p491

Aside  from some  minor  differences in  pin  configuration, the  main
difference is the direct support  for 3.3V processors. This chipset is
still a 5V part. The cache operates at bus speed, max 66MHz.


This  chip was  used on  the Pentium  90MHz CPU  complexes of  Intel's
Xpress  platform.   Specifically  the BXCPUPENT90  (Single  90MHz,  16
82492s). Also found on IBM 9595/Server 500 Pentium 90MHz complexes.

***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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*VLSI...
**VL82C481         System/Cache/ISA bus Controller                 c92
***Basics:...
***Info:...
***differences to the VL82C480:
"It  also  supports  486  family   CPUs  that  contain  an  integrated
write-back cache (P24T, etc.)"

"It can also  perform 3-2-2-2 cycle reads for support  of slower SRAMs
at higher frequences."

"The HITM#  input is provided to  force the VL82C481 to  abort DRAM or
cache cycles when a hit on a dirty line in the CPU write-back cache is
detected. the DRAM or cache  cycle is subsequently restarted after the
CPU has written back the dirty data"

"Further support for devices that reside  on the local bus is provided
through use of the <*LDEV#*> (Local Bus Access) input, which deselects
the VL82C481 during  CPU cycles <*and causes the  VL82C481 to generate
VL-Bus  memory  cycles  when  active  dur- ing  DMA  and  Master  Mode
cycles*>."

[areas  marked <*  *> are  differences or  additions, in  the VL82C480
LDEV# is LBA#]

<*On power-on  default,*> The  chip does not  generate parity  for CPU
writes to DRAM, but does  generate cache write-back cycles. <*However,
a mode is  provided in which the VL82C481 will  generate parity during
either CPU writes or VL master writes.*>

[areas marked <* *> are additions]

***Configurations:...
***Features:...
**VL82C486         Single-Chip 486, SC486, Controller                ?...
**VL82C425         486 Cache controller                              ?...
**????????         Cheetah 486, PCI [no datasheet]                   ?...
**VL82C3216        Bus Expanding Controller Cache with write buffer  ?...
**VL82C521/522     Lynx/M                                            ?...
**VL82C530         Eagle Ð                                         c95...
**VL82C541/543     Lynx                                            c95...
**VL82C591/593     SuperCore 590                                   c94...
**VL82C594/596/597 Wildcat                                         c95...
**I/O Chips:
**VL82C106 Combination I/O chip                                      ?...
**VL82C107 SCAMP  Combination I/O chip                               ?...
**VL82C108 TOPCAT Combination I/O chip                               ?...
**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
**Video: ...
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**Other:...
**Not sure if they actually exist...
*Western Digital...
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*General Sources:...