[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:
Date source: 1995_Intel_Pentium_Processors_and_Related_Components.pdf

Information taken from: 
            1995_Intel_Pentium_Processors_and_Related_Components.pdf*
                                         8249x Cache controllers.pdf**
>*  Datasheet dated Nov'94
>** Datasheet undated, whole document dated '95

The info and features section have  been solely sourced from the first
source.   The  second source  provides  far  more detail.   Additional
information in the configurations section  and below have been sourced
from the second.

"Although the 82497 Cache Controller  is part of the Pentium processor
(735\90, 815\100, 1000\120, 1110\133) CPU-Cache Chip Set and the 82496
Cache  Controller is part  of the  Pentium Processor  (510\60, 567\66)
Chip  Set, the  two parts  are functionally  identical except  for the
differences noted in this section." - p491

Aside  from some  minor  differences in  pin  configuration, the  main
difference is the direct support  for 3.3V processors. This chipset is
still a 5V part. The cache operates at bus speed, max 66MHz.


This  chip was  used on  the Pentium  90MHz CPU  complexes of  Intel's
Xpress  platform.   Specifically  the BXCPUPENT90  (Single  90MHz,  16
82492s). Also found on IBM 9595/Server 500 Pentium 90MHz complexes.

***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C480         System/Cache/ISA bus Controller                   ?
***Info:...
***Configurations:...
***Features:
o   Fully compatible with 486-based ISA bus systems
o   Power-on reset option selects various operational modes
o   Up to 40 MHz CPU operation
o   Replaces the following peripheral logic on the motherboard:
    - Two 82C37A DMA controllers
    - 74LS612 memory mappers (extended to support 64 MB)
    - Two 82C59A interrupt controllers
    - 82C54 timer
    - 82284 clock generator and ready interface
    - 82288 bus controller
o   Memory controller features include:
    - Up to 64 MB system memory
    - 256K, 1M or 4M DRAM
    - Double-sided SIMMs
    - Page Mode DRAM access
    - Two-way interleave support
    - Programmable RAS#/CAS# timing
    - Burst read and write support
    - Parity generation/checking for on-board DRAM
    - Staggered RAS# refresh
o   Supports:
    - One to four banks 32 bits wide
    - 8- or 16-bit wide BIOS ROM
    - shadow RAM in the 640K-1M area
    - Asynchronous ISA bus operation up to 16 MHz
    - Relocation of slot ROMs
    - Access to devices residing on the local bus
    - Weitek 4167 numeric coprocessor
o   0.8-micron CMOS technology
o   208-lead MQFP (metric quad flat pack)
o   Includes:
    - Memory/refresh controller
    - Port A, B, and NMI logic
    - Bus steering logic
    - Turbo control
    - hidden refresh
    - Three-stateable outputs for board testing
o   Selectable slow DRAM refresh saves power
o   On-chip write-back cache controller:
    - External tags
    - Direct map
    - Separate "dirty" RAM not required
    - 2-1-1-1 reads with two banks, 2-2-2-2 with one bank
    - 32 KB to 1MB cache size
    - One wait state writes on cache-hits
    - Optional zero wait state writes
    - Optional one wait state reads
o   Other features:
    - Programmable for 10- or 16-bit internal I/O addressing
    - Programmable drive on the DRAM and ISA bus signals
    - Programmable memory access to define "fast-bus", local bus, slot
      bus, non-cacheable and write-protect areas
    - Input pin defines access to local bus devices

**VL82C481         System/Cache/ISA bus Controller                 c92...
**VL82C486         Single-Chip 486, SC486, Controller                ?...
**VL82C425         486 Cache controller                              ?...
**????????         Cheetah 486, PCI [no datasheet]                   ?...
**VL82C3216        Bus Expanding Controller Cache with write buffer  ?...
**VL82C521/522     Lynx/M                                            ?...
**VL82C530         Eagle Ð                                         c95...
**VL82C541/543     Lynx                                            c95...
**VL82C591/593     SuperCore 590                                   c94...
**VL82C594/596/597 Wildcat                                         c95...
**I/O Chips:
**VL82C106 Combination I/O chip                                      ?...
**VL82C107 SCAMP  Combination I/O chip                               ?...
**VL82C108 TOPCAT Combination I/O chip                               ?...
**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...