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**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:
o   High Performance Second Level Cache
    - Zero Wait States at 66 MHz 
    - Two-Way Set Associative 
    - Writeback with MESI Protocol 
    - Concurrent CPU Bus and Memory Bus Operation 
    - Boundary Scan
o   Pentium Processor (735\90, 815\100)
    - Chip Set Version of Pentium Processor (735\90, 815\100) 
    - Superscalar Architecture -
    - Enhanced Floating Point 
    - On-Chip 8K Code and 8K Data Caches
    - See Pentium Processor Family Data Book for More Information
o   Highly Flexible
    - 256K to 512K with Parity
    - 32-, 64-, or 128-Bit Wide Memory Bus
    - Synchronous, Asynchronous and Strobed Memory Bus Operation
    - Selectable Bus Widths, Line Sizes, Transfers and Burst Orders
o   Full Multiprocessing Support
    - Concurrent CPU, Memory Bus and Snoop Operations
    - Complete MESI Protocol
    - Internal/External Parity Generation/Checking
    - Supports Read For Ownership, Write-Allocation and Cache-to-Cache
      Transfers

**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**TACT83000   AT 'Tiger' Chip Set (386)                            c89
***Info:...
***Configurations:...
***Features:
o   High-Speed 1-um CMOS Technology Supports System Speeds up to 
    33 MHz
o   Fully AT-Compatible 386 Three-Chip SX, Four-Chip DX Solutions
o   Only Four Additional Logic Chips Needed
o   Major Features Programmable Through Software
o   TACT83442 Memory Control Unit (MCU)
    - Cascadable up to Eight Devices
    - Address Range of up to 32M Byte Per Device, 256M Byte Fully 
      Cascaded
    - Supports 256K-, 1M-, and 4M-Bit DRAMs in Normal, Page, Word-
      interleave, and Page Block-interleave Modes
    - Programmable DRAM Timing Parameters
    - Supports up to Two Memory Banks for 32-Bit Systems and Four 
      Banks for 16-Bit Systems
    - Can Directly Drive up to 36 DRAM Devices
    - Shadow RAM Available Between 0C 0000h and 0F FFFFh
    - Contains Global Page Mapping RAM Allowing Remap of 
      - 64K-Byte Memory Blocks Above 1M Byte
      - 16K-Byte Memory Blocks Below 1M Byte
o   TACT83443 AT Bus Interface Unit (ATU)
    - Internal Clock Switching Between Two Independent Frequencies 
      Controlled by Software
    - Asynchronous AT Bus Interface With Write Buffer Option
    - Full AT Direct-Drive Capability
    - Extended Direct Memory Access Mode for 32-Bit Operation
    - Fast CPU Reset and A20 GATE Modification
    - Numeric Processor Interface for 387SX, 387DX, and Weitek 3167
    - Integrates All Essential AT Peripherals
    - Real Time Clock With 128-Byte CMOS RAM
o   TACT83441 Data Path Unit (DPU)
    - 8- and 16-Bit Data Bus Sizing
    - Data Path Cascadable to 32 Bits
    - Write Buffer Capability for AT Bus Access
    - Supports Posted Write Operations From Cache Controller
    - Parity Generation and Checking Logic

**TACT84500   AT Chip Set (486, EISA) [no datasheet, some info]    c91...
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