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**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:
o   High Performance Second Level Cache
    - Zero Wait States at 66 MHz 
    - Two-Way Set Associative 
    - Writeback with MESI Protocol 
    - Concurrent CPU Bus and Memory Bus Operation 
    - Boundary Scan
o   Pentium Processor (735\90, 815\100)
    - Chip Set Version of Pentium Processor (735\90, 815\100) 
    - Superscalar Architecture -
    - Enhanced Floating Point 
    - On-Chip 8K Code and 8K Data Caches
    - See Pentium Processor Family Data Book for More Information
o   Highly Flexible
    - 256K to 512K with Parity
    - 32-, 64-, or 128-Bit Wide Memory Bus
    - Synchronous, Asynchronous and Strobed Memory Bus Operation
    - Selectable Bus Widths, Line Sizes, Transfers and Burst Orders
o   Full Multiprocessing Support
    - Concurrent CPU, Memory Bus and Snoop Operations
    - Complete MESI Protocol
    - Internal/External Parity Generation/Checking
    - Supports Read For Ownership, Write-Allocation and Cache-to-Cache
      Transfers

**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82c801         SCWB2 DX Single Chip Solution                    c:92
***Notes:...
***Info:...
***Configurations:...
***Features:
o   Supports 486 SX/DX/DX2 and 487SX 
o   Single chip PC/AT solution: one 208 pin CMOS plastic flat package 
o   1 X and 2X clock source, supporting systems running from 16 
    to 50 MHz 
o   Write back direct mapped, bank interleave cache 
    with size selections: 64, 128, 256, and 512K 
o   Supports 2-1-1-1, 3-1-1-1, 2-2-2-2
,   and 3-2-2-2 cache burst cycles 
o   Programmable cache and DRAM read/write cycles 
o   Built in TAG auto invalidation circuitry 
o   Programmable cache and DRAM read/write cycles 
o   Supports eight banks of 256K, 1 M, and 4M DRAMs for 
    configurations up to 64MB 
o   Supports 3-2-2-2 DRAM burst cycles 
o   Hidden refresh, slow refresh, and CAS before RAS refresh 
    supported 
o   Comprehensive VESA VL and OPTi high performance local bus 
    support 
o   Low power, high speed 0.8u CMOS technology 
o   Integrated peripherals controller 

**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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