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*Forex . . . . . . [List only, no datasheets found]
FRX36C200/100 386
FRX36C300/200 386 Write Through
FRX36C300/46C402 386 Write Through
FRX36C311 Single Chip 386SX with Cache
FRX46C411/402 386 Write Through
FRX46C411/412 386 Write Through
FRX46C421A/422 386 Write Back
FRX46C521A ?
FRX58C613/601A ?
FRX58C613A/602B/601B ?
*Intel...
*Headland/G2...
*HMC (Hulon Microelectronics)
**HMC82C206 Integrated Peripherals Controller (10MHz C&T 82c206) ?...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)
**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers <84...
**TACT82000 3-Chip 286 [no datasheet] c89...
**TACT82411 Snake Single-Chip AT Controller c90...
**TACT82S411 Snake+ Single-Chip AT Controller [no datasheet] c91...
**TACT83000 AT 'Tiger' Chip Set (386) c89...
**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91...
**Other:...
*UMC
**UM82C*** (IBM/INTEL Direct replacement) c87
Note: Dates vary for when these chips were first available. Two
databooks have been used one from '86 the other from '91. Not all the
chips are listed in the '86 databook, the date of '87 is an
assumption.
PC/XT:
IBM: UMC: Desc:
Intel 8284 UM82C84A 25MHz CMOS Clock Generator and Driver
Intel 8288 UM82C88 Bus Controller
Intel 8259 UM8259A Programmable Interrupt Controller also UM82C59A-2 (CMOS version)
Intel 8237 UM8237A 3-5MHz Programmable DMA Controller (DMAC)
Intel 8253 UM8253*2 2.6-5MHz Programmable Interval Timer
Intel 8255 UM82C55A* Programmable Peripheral Interface
Note: * indicates: possible compatibility, datasheet does not state
explicitly. YMMV.
Note: *2 indicates: The UM8253 can be replaced with the
UM82C54/-2. The datasheet says it is a superset of the 8253, and
works up to 10MHz. Also it's compatible with the 8254. AT: IBM:
UMC: Desc: Intel 82284 UM82C284* 10-12.5MHz Clock Generator and
Ready Interface Intel 82288 UM82C288* 10-12.5MHz Bus Controller
Intel 8254 UM82C54/-2 8-10MHz CMOS Programmable Interval Timer
Intel 8259 UM8259A Programmable Interrupt Controller also
UM82C59A-2 (CMOS version) Intel 8237 UM8237A 3-5MHz Programmable
DMA Controller (DMAC) 74LS612 UM74HCT612* Memory Mapper MC146818
RTC UM82C6818* Real-Time Clock (RTC) Intel 8047 ?? Keyboard
Controller
Note: * indicates: possible compatibility, datasheet does not state
explicitly. YMMV.
**UM82C088 PC/XT Integration Chip <91...
**UM82C230 286AT MORTAR Chip Set <91...
**UM82C210 386SX/286 AT Chip Set <91...
**UM82C3xx Twinstar & UM82C336F/N & UM82C39x [no datasheet] ?...
**UM82C380 386 HEAT PC/AT Chip Set <91...
**UM82C480 386/486 PC Chip Set c91
***Info:...
***Configurations:...
***Features:...
**UM82C493/491 ??????????????? [no datasheet] ?...
**UM8498/8496 486 VL Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886 HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890 Pentium chipset [no datasheet] ?...
**
**Support Chips:
**UM82152 Cache Controller (AUStek A38152 clone) <91...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91
***Info:...
***Versions:...
***Features:...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
*Unresearched:...
*VIA
**SL9XXX FlexSet family General information...
**SL9011 System Controller (80286/80386SX/DX, 16/20/25MHz) <Jan90...
**SL9020 Data Controller <Jan90...
**SL9025 Address Controller <Jan90...
**SL9030 Integrated Peripheral Controller <Jan90...
**SL9090/A Universal PC/AT Clock Chip <oct88...
**SL9095 Power Management Unit ?...
**SL9151 80286 Page Interleave Memory Controller (16-25MHz) ?...
**SL9250 80386SX Page Mode Memory Controller (16/20MHz 8MB) ?...
**SL9251 80386SX Page Interleave Memory Controller <04/13/90...
**SL9252 80386SX System and Memory Controller <06/12/90...
**SL9350 80386DX Page Mode Memory Controller (16-25MHz 16MB) ?...
**SL9351 80386DX Page Interleave Memory Controller (33MHz) ?...
**SL9352 80386DX System and Memory Controller <06/12/90...
**SLXXXX Other chips...
**
**VT82C470 "Jupiter", Chip Set (w/o cache) 386 [no datasheet] ?
**VT82C475 "Jupiter", Chip Set (w/cache) 386 [no datasheet] ?
**VT82C486/2/3 "GMC chipset" [no datasheet, some info] ?...
**VT82C495/480 "Venus" Chip Set [no datasheet] ?
**VT82C495/491 ? EISA Chip Set [no datasheet, some info] <93...
**VT82C496G Pluto, Green PC 80486 PCI/VL/ISA System <05/30/94...
**VT82C530MV 3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M Apollo Master, Green Pentium/P54C <06/22/95...
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97
***Info:
The Apollo-VP3 is a high performance, cost-effective and energy
efficient chip set for the implementation of AGP / PCI / ISA desktop
and notebook personal computer systems based on 64-bit Socket-7 (Intel
Pentium and Pentium MMX; AMD K5 / 5k86 and K6 / 6k86; and Cyrix / IBM
6x86 / M2) super-scalar processors.
The Apollo-VP3 chip set consists of the VT82C597 system controller
(472 pin BGA) and the VT82C586B PCI to ISA bridge (208 pin PQFP). The
VT82C597 system controller provides superior performance between the
CPU, optional synchronous cache, DRAM, AGP bus, and PCI bus with
pipelined, burst, and concurrent operation. For pipelined burst
synchronous SRAMs, 3-1-1-1-1-1-1-1 timing can be achieved for both
read and write transactions at 66 MHz. Four cache lines (16
quadwords) of CPU/cache to DRAM write buffers with concurrent
write-back capability are included on chip to speed up cache read and
write miss cycles.
The VT82C597 supports six banks of DRAMs up to 1GB. The DRAM
controller supports standard Fast Page Mode (FPM) DRAM, EDO-DRAM,
Synchronous DRAM (SDRAM), and SDRAM-II with Double Data Rate (DDR) in
a flexible mix / match manner. The Synchronous DRAM interface allows
zero wait state bursting between the DRAM and the data buffers at
66Mhz. The six banks of DRAM can be composed of an arbitrary mixture
of 1M / 2M / 4M / 8M / 16MxN DRAMs. The DRAM controller also supports
optional ECC (single-bit error correction and multi-bit detection) or
EC (error checking) capability separately selectable on a bank-by-bank
basis.
The VT82C597 also supports full AGP v1.0 capability for maximum bus
utilization including 2x mode transfers, SBA (SideBand Addressing),
Flush/Fence commands, and pipelined grants. An eight level request
queue plus a four level post-write request queue with thirty-two and
sixteen quadwords of read and write data FIFO's respectively are
included for deep pipelined and split AGP transactions. A
single-level GART TLB with 16 full associative entries and flexible
CPU/AGP/PCI remapping control is also provided for operation under
protected mode operating environments.
The VT82C597 supports two 32-bit 3.3 / 5V system buses (one AGP and
one PCI) with 64-bit to 32-bit data conversion. The 82C597 also
contains a built-in bus-to-bus bridge to allow simultaneous concurrent
operations on each bus. Five levels (doublewords) of post write
buffers are included to allow for concurrent CPU and PCI operation.
Consecutive CPU addresses are converted into burst PCI cycles with
byte merging capability for optimal CPU to PCI throughput. For PCI
master operation, forty-eight levels (doublewords) of post write
buffers and sixteen levels (doublewords) of prefetch buffers are
included for concurrent PCI bus and DRAM/cache accesses. The chipset
also supports enhanced PCI bus commands such as Memory-Read-Line,
Memory-Read-Multiple and Memory-Write-Invalid commands to minimize
snoop overhead. In addition, the chipset supports advanced features
such as snoop ahead, snoop filtering, L1 write-back forward to PCI
master and L1 write-back merged with PCI post write buffers to
minimize PCI master read latency and DRAM utilization. The VT82C586B
PCI to ISA bridge supports four levels (doublewords) of line buffers,
type F DMA transfers and delay transaction to allow efficient PCI bus
utilization and (PC I-2.1 compliant). The VT82C586B also includes an
integrated keyboard controller with PS2 mouse support, integrated
DS12885 style real time clock with extended 256 byte CMOS RAM,
integrated master mode enhanced IDE controller with full scatter and
gather capability and extension to UltraDMA-33 / ATA-33 for 33MB/sec
transfer rate, integrated USB interface with root hub and two function
ports with built-in physical layer transceivers, Distributed DMA
support, and OnNow / ACPI compliant advanced configuration and power
management interface. A complete main board can be implemented with
only six TTLs.
The Apollo VP3 chipset is ideal for high performance, high quality,
high energy efficient and high integration desktop and notebook AGP /
PCI / ISA computer systems.
***Configurations:...
***Features:...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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