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*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
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*Forex . . . . . . [List only, no datasheets found]
FRX36C200/100 386
FRX36C300/200 386 Write Through
FRX36C300/46C402 386 Write Through
FRX36C311 Single Chip 386SX with Cache
FRX46C411/402 386 Write Through
FRX46C411/412 386 Write Through
FRX46C421A/422 386 Write Back
FRX46C521A ?
FRX58C613/601A ?
FRX58C613A/602B/601B ?
*Intel...
*Headland/G2...
*HMC (Hulon Microelectronics)
**HMC82C206 Integrated Peripherals Controller (10MHz C&T 82c206) ?...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)
**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers <84...
**TACT82000 3-Chip 286 [no datasheet] c89...
**TACT82411 Snake Single-Chip AT Controller c90...
**TACT82S411 Snake+ Single-Chip AT Controller [no datasheet] c91...
**TACT83000 AT 'Tiger' Chip Set (386) c89...
**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91...
**Other:...
*UMC
**UM82C*** (IBM/INTEL Direct replacement) c87
Note: Dates vary for when these chips were first available. Two
databooks have been used one from '86 the other from '91. Not all the
chips are listed in the '86 databook, the date of '87 is an
assumption.
PC/XT:
IBM: UMC: Desc:
Intel 8284 UM82C84A 25MHz CMOS Clock Generator and Driver
Intel 8288 UM82C88 Bus Controller
Intel 8259 UM8259A Programmable Interrupt Controller also UM82C59A-2 (CMOS version)
Intel 8237 UM8237A 3-5MHz Programmable DMA Controller (DMAC)
Intel 8253 UM8253*2 2.6-5MHz Programmable Interval Timer
Intel 8255 UM82C55A* Programmable Peripheral Interface
Note: * indicates: possible compatibility, datasheet does not state
explicitly. YMMV.
Note: *2 indicates: The UM8253 can be replaced with the
UM82C54/-2. The datasheet says it is a superset of the 8253, and
works up to 10MHz. Also it's compatible with the 8254. AT: IBM:
UMC: Desc: Intel 82284 UM82C284* 10-12.5MHz Clock Generator and
Ready Interface Intel 82288 UM82C288* 10-12.5MHz Bus Controller
Intel 8254 UM82C54/-2 8-10MHz CMOS Programmable Interval Timer
Intel 8259 UM8259A Programmable Interrupt Controller also
UM82C59A-2 (CMOS version) Intel 8237 UM8237A 3-5MHz Programmable
DMA Controller (DMAC) 74LS612 UM74HCT612* Memory Mapper MC146818
RTC UM82C6818* Real-Time Clock (RTC) Intel 8047 ?? Keyboard
Controller
Note: * indicates: possible compatibility, datasheet does not state
explicitly. YMMV.
**UM82C088 PC/XT Integration Chip <91...
**UM82C230 286AT MORTAR Chip Set <91...
**UM82C210 386SX/286 AT Chip Set <91...
**UM82C3xx Twinstar & UM82C336F/N & UM82C39x [no datasheet] ?...
**UM82C380 386 HEAT PC/AT Chip Set <91...
**UM82C480 386/486 PC Chip Set c91
***Info:...
***Configurations:...
***Features:...
**UM82C493/491 ??????????????? [no datasheet] ?...
**UM8498/8496 486 VL Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886 HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890 Pentium chipset [no datasheet] ?...
**
**Support Chips:
**UM82152 Cache Controller (AUStek A38152 clone) <91...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91
***Info:...
***Versions:...
***Features:...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
*Unresearched:...
*VIA
**SL9XXX FlexSet family General information...
**SL9011 System Controller (80286/80386SX/DX, 16/20/25MHz) <Jan90...
**SL9020 Data Controller <Jan90...
**SL9025 Address Controller <Jan90...
**SL9030 Integrated Peripheral Controller <Jan90...
**SL9090/A Universal PC/AT Clock Chip <oct88...
**SL9095 Power Management Unit ?...
**SL9151 80286 Page Interleave Memory Controller (16-25MHz) ?...
**SL9250 80386SX Page Mode Memory Controller (16/20MHz 8MB) ?...
**SL9251 80386SX Page Interleave Memory Controller <04/13/90...
**SL9252 80386SX System and Memory Controller <06/12/90...
**SL9350 80386DX Page Mode Memory Controller (16-25MHz 16MB) ?...
**SL9351 80386DX Page Interleave Memory Controller (33MHz) ?...
**SL9352 80386DX System and Memory Controller <06/12/90...
**SLXXXX Other chips...
**
**VT82C470 "Jupiter", Chip Set (w/o cache) 386 [no datasheet] ?
**VT82C475 "Jupiter", Chip Set (w/cache) 386 [no datasheet] ?
**VT82C486/2/3 "GMC chipset" [no datasheet, some info] ?...
**VT82C495/480 "Venus" Chip Set [no datasheet] ?
**VT82C495/491 ? EISA Chip Set [no datasheet, some info] <93...
**VT82C496G Pluto, Green PC 80486 PCI/VL/ISA System <05/30/94...
**VT82C530MV 3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M Apollo Master, Green Pentium/P54C <06/22/95...
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97
***Notes:...
***Info:...
***Configurations:...
***Features:
o Flexible CPU Interface
- Supports 64-bit Pentium, AMD 5k86, AMD 6k86 and Cyrix 6x86 CPUs
- CPU external bus speed up to 75 MHz (asynchronous) or 66MHz
(synchronous) (internal 200Mhz and above)
- Supports CPU internal write-back cache
- System management interrupt, memory remap and STPCLK mechanism
- Cyrix 6x86 linear burst support
- CPU NA# / Address pipeline capability
o Low Cost
- PQFP packaging for low-cost implementation of 64-bit Pentium-
CPU, 64-bit system memory, and 32-bit PCI
- VT82C580 Apollo VPX Chipset: VT82C585VPX system controller and
VT82C587VP Data Buffers
- VT82C586B includes UltraDMA-33 EIDE, USB, and Keyboard / Mouse
Interfaces plus RTC / CMOS
- Six TTLs for a complete main board implementation
o PCI/ISA Green PC Ready
- Supports 3.3V or 5V interface to CPU, system memory, and / or
PCI bus
- Supports CPUs with internal voltages below 3.3V
- PC-97 compatible using VT82C586B South Bridge with ACPI
Power Management
o Advanced Cache Controller
- Direct map write back or write through secondary cache
- Pipelined burst synchronous SRAM (PBSRAM) cache support
- Flexible cache size: 0K/256K/512K/1M/2MB
- 32 byte line size to match the primary cache
- Integrated 10-bit tag comparator
- 3-1-1-1 read/write timing for PBSRAM access at 66/75 MHz
- 3-1-1-1-1-1-1-1 back to back read timing for PBSRAM access
at 66/75 MHz
- Sustained 3 cycle write access for PBSRAM access or CPU to
DRAM and PCI bus post write buffers at 66/75 MHz
- Data streaming for simultaneous primary and secondary cache
line fill
- System and video BIOS cacheable and write-protect
- Programmable cacheable region and cache timing
o Fast DRAM Controller
- Fast Page Mode/EDO/Synchronous-DRAM support in a mixed
combination
- Mixed 1M/2M/4M/8M/16MxN DRAMs
- 6 banks up to 512MB DRAMs
- Flexible row and column addresses
- 64-bit or 32-bit data width in arbitrary mixed combination
- 3.3v and 5v DRAM without external buffers
- Two-bank interleaving for 16Mbit SDRAM support
- Two-bank and four bank interleaving for 64Mbit SDRAM support
(14 MA lines)
- Four cache lines (16 quadwords) of CPU/cache to DRAM write
buffers
- Concurrent DRAM writeback
- Speculative DRAM access
- Read around write capability for non-stalled CPU read
- Burst read and write operation
- 4-2-2-2 on page, 7-2-2-2 start page and 9-2-2-2 off page timing
for EDO DRAMs at 50/60 MHz
- 5-2-2-2 on page, 8-2-2-2 start page and 11-2-2-2 off page timing
for EDO DRAMs at 66 MHz
- 6-1-1-1 on page, 8-1-1-1 start page and 10-1-1-1 off page for
SDRAMs at 66 MHz
- 5-2-2-2-3-1-2-2 back-to-back access for EDO DRAM at 66 MHz
- 6-1-1-1-3-1-1-1 back-to-back access for SDRAM at 66 MHz
- BIOS shadow at 16KB increment
- Decoupled and burst DRAM refresh with staggered RAS timing
- Programmable refresh rate, CAS-before-RAS refresh and refresh
on populated banks only
o Intelligent PCI Bus Controller
- 32 bit 3.3/5v PCI interface
- Synchronous divide-by-two and asynchronous PCI bus interface
- PCI master snoop ahead and snoop filtering
- PCI master peer concurrency
- Synchronous bus to CPU clock with divide-by-two from the CPU
clock
- Automatic detection of data streaming burst cycles from CPU to
the PCI bus
- Five levels (double-words) of CPU to PCI posted write buffers
- Byte merging in the write buffers to reduce the number of PCI
cycles and to create further PCI bursting possibilities
- Zero wait state PCI master and slave burst transfer rate
- PCI to system memory data streaming up to 132Mbyte/sec
- Forty-eight levels (double-words) of post write buffers from
PCI masters to DRAM
- Sixteen levels (double-words) of prefetch buffers from DRAM
for access by PCI masters
- Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
- Complete steerable PCI interrupts
- Supports L1 write-back forward to PCI master read to minimize
PCI read latency
- Supports L1 write-back merged with PCI master post-write to
minimize DRAM utilization
- Provides transaction timer to fairly arbitrate between PCI
masters
- PCI-2.1 compliant
o Built-in nand-tree pin scan test capability
o 0.6um mixed voltage, high speed / low power CMOS process
o VT82C585VPX: 208-pin PQFP Package
o VT82C587VP: 100-pin PQFP Package
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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