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*Forex . . . . . . [List only, no datasheets found]
FRX36C200/100         386
FRX36C300/200         386 Write Through
FRX36C300/46C402      386 Write Through
FRX36C311             Single Chip 386SX with Cache
FRX46C411/402         386 Write Through
FRX46C411/412         386 Write Through
FRX46C421A/422        386 Write Back
FRX46C521A            ?
FRX58C613/601A        ?
FRX58C613A/602B/601B  ?

*Intel...
*Headland/G2...
*HMC (Hulon Microelectronics)
**HMC82C206 Integrated Peripherals Controller (10MHz C&T 82c206)     ?...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)
**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers          <84...
**TACT82000   3-Chip 286 [no datasheet]                            c89...
**TACT82411   Snake  Single-Chip AT Controller                     c90...
**TACT82S411  Snake+ Single-Chip AT Controller [no datasheet]      c91...
**TACT83000   AT 'Tiger' Chip Set (386)                            c89...
**TACT84500   AT Chip Set (486, EISA) [no datasheet, some info]    c91...
**Other:...
*UMC
**UM82C***     (IBM/INTEL Direct replacement)                      c87
Note:  Dates vary  for when  these  chips were  first available.   Two
databooks have been used one from  '86 the other from '91. Not all the
chips  are  listed  in  the  '86  databook, the  date  of  '87  is  an
assumption.

PC/XT:
IBM:	      UMC:	  Desc:
Intel 8284    UM82C84A    25MHz CMOS Clock Generator and Driver
Intel 8288    UM82C88     Bus Controller
Intel 8259    UM8259A     Programmable Interrupt Controller also UM82C59A-2 (CMOS version)
Intel 8237    UM8237A     3-5MHz Programmable DMA Controller (DMAC)
Intel 8253    UM8253*2    2.6-5MHz Programmable Interval Timer
Intel 8255    UM82C55A*   Programmable Peripheral Interface

Note: *  indicates: possible  compatibility, datasheet does  not state
      explicitly. YMMV.

Note: *2  indicates:   The   UM8253   can   be   replaced   with   the
      UM82C54/-2. The datasheet says it is a superset of the 8253, and
      works up to 10MHz. Also it's compatible with the 8254.  AT: IBM:
      UMC: Desc: Intel 82284  UM82C284* 10-12.5MHz Clock Generator and
      Ready Interface Intel 82288  UM82C288* 10-12.5MHz Bus Controller
      Intel 8254  UM82C54/-2 8-10MHz CMOS Programmable  Interval Timer
      Intel  8259  UM8259A   Programmable  Interrupt  Controller  also
      UM82C59A-2 (CMOS version) Intel 8237 UM8237A 3-5MHz Programmable
      DMA Controller (DMAC) 74LS612 UM74HCT612* Memory Mapper MC146818
      RTC  UM82C6818* Real-Time  Clock (RTC)  Intel 8047  ??  Keyboard
      Controller

Note: *  indicates: possible  compatibility, datasheet does  not state
explicitly. YMMV.

**UM82C088     PC/XT Integration Chip                              <91...
**UM82C230     286AT MORTAR Chip Set                               <91...
**UM82C210     386SX/286 AT Chip Set                               <91...
**UM82C3xx     Twinstar & UM82C336F/N & UM82C39x [no datasheet]      ?...
**UM82C380     386 HEAT PC/AT Chip Set                             <91...
**UM82C480     386/486 PC Chip Set                                 c91
***Info:...
***Configurations:...
***Features:...
**UM82C493/491 ??????????????? [no datasheet]                        ?...
**UM8498/8496  486 VL Chipset  "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886  HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890       Pentium chipset [no datasheet]                        ?...
**
**Support Chips:
**UM82152      Cache Controller (AUStek A38152 clone)              <91...
**UM82C852     Multi I/O For XT                                    <91...
**UM82C206     Integrated Peripheral Controller                    <91
***Info:...
***Versions:...
***Features:...
**UM82c45x     Serial/Parallel chips                                 ?...
**Other chips:...
*Unresearched:...
*VIA
**SL9XXX   FlexSet family General information...
**SL9011   System Controller (80286/80386SX/DX, 16/20/25MHz)    <Jan90...
**SL9020   Data Controller                                      <Jan90...
**SL9025   Address Controller                                   <Jan90...
**SL9030   Integrated Peripheral Controller                     <Jan90...
**SL9090/A Universal PC/AT Clock Chip                           <oct88...
**SL9095   Power  Management Unit                                    ?...
**SL9151   80286 Page Interleave Memory Controller (16-25MHz)        ?...
**SL9250   80386SX Page Mode Memory Controller (16/20MHz 8MB)        ?...
**SL9251   80386SX Page Interleave Memory Controller         <04/13/90...
**SL9252   80386SX System and Memory Controller              <06/12/90...
**SL9350   80386DX Page Mode Memory Controller (16-25MHz 16MB)       ?...
**SL9351   80386DX Page Interleave Memory Controller (33MHz)         ?...
**SL9352   80386DX System and Memory Controller              <06/12/90...
**SLXXXX   Other chips...
**
**VT82C470     "Jupiter", Chip Set (w/o cache) 386 [no datasheet]    ?
**VT82C475     "Jupiter", Chip Set (w/cache) 386   [no datasheet]    ?
**VT82C486/2/3 "GMC chipset"            [no datasheet, some info]    ?...
**VT82C495/480 "Venus" Chip Set                    [no datasheet]    ?
**VT82C495/491 ? EISA Chip Set          [no datasheet, some info]  <93...
**VT82C496G    Pluto, Green PC 80486 PCI/VL/ISA System       <05/30/94...
**VT82C530MV   3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M    Apollo Master, Green Pentium/P54C             <06/22/95
***Info:...
***Configurations:...
***Features:
o   PCI/ISA Green PC Ready
o   High Integration
    - VT82C575M system controller
    - VT82C576M PCI bus controller
    - Two instances of the VT82C577M data buffers
    - Glueless interface to the VT82C416 integrated clock generator, 
      real time clock with extended CMOS, plug and play control and 
      keyboard controller with PS/2 mouse support
    - Ten TTLs for a complete main board implementation
o   Flexible CPU Interface
    - 64-bit P54C, Pentium, K5 and M1 CPU interface
    - 3.3v or 5v CPU and cache interface
    - CPU external bus speed up to 66Mhz (internal 150Mhz and above)
    - Supports CPU internal write-back cache
    - Concurrent CPU/cache and PCI/DRAM operation
    - System management interrupt, memory remap and STPCLK mechanism
    - Cyrix M1 linear burst support
    - CPU NA#/Address pipeline capability
o   Advanced Cache Controller
    - Direct map write back or write through secondary cache
    - Burst Synchronous (Pipelined or non-pipelined), asynchronous 
      SRAM and Cache Module support
    - Eight-pin CWE# and GWE# control options
    - Flexible cache size: 0K/128K/256K/512K/1M/2MB
    - 32 byte line size to match the primary cache
    - Integrated 10-bit tag comparator
    - Interleaved SRAM access
    - 3-1-1-1 read/write timing for Burst Synchronous SRAM access 
      at 66Mhz
    - 3-2-2-2 (read) and 4-2-2-2 (write) timing for interleaved 
      asynchronous SRAM access at 66Mhz
    - Data streaming for simultaneous primary and secondary cache 
      line fill
    - System and video BIOS cacheable and write-protect
    - Programmable cacheable region and cache timing
    - Optional combined tag and alter bit SRAM for write-back scheme
o   Fast DRAM Controller
    - Concurrent DRAM Writeback
    - Four levels of CPU/cache to DRAM write buffer
    - Standard Page Mode/EDO/Burst EDO-DRAM support in a flexible/
      mixed combination
    - EDO-DRAM auto-detect
    - Mixed 256K/512K/1M/2M/4M/8M/16MxN DRAMs
    - 8 banks up to 512MB DRAMs
    - Flexible row and column addresses
    - 64 bit or 32 bit data width
    - Burst read and write operation
    - Programmable DRAM timing
    - BIOS shadow at 16KB increment
    - System management memory remapping
    - Decoupled and burst DRAM refresh with staggered RAS timing
    - CAS-before-RAS refresh timing
o   Intelligent PCI Bus Controller
    - 32 bit PCI interface
    - PCI Master snoop ahead and snoop filtering
    - Concurrent PCI master/CPU/IDE operations
    - Synchronous Bus to CPU clock with divide-by-two from the CPU 
      clock
    - Multiple accelerated schemes for high bus throughput
    - Automatic detection of data streaming burst cycles from CPU to 
      the PCI bus
    - Four level of CPU to PCI posted write buffers
    - Byte merging in the write buffers to reduce the number of PCI 
      cycles and to create further PCI bursting possibilities
    - PCI to system memory data streaming up to 110Mbyte/sec
    - Four level of post write buffers from PCI masters to DRAM
    - Four level of prefetch buffers from DRAM for access by PCI 
      masters
    - Zero wait state PCI master and slave burst transfer rate
    - Complete steerable PCI interrupts
    - IDE and ISA bus through peer PCI bus to avoid slower traffic 
      blocking the regular PCI bus
    - PCI-2.1 compliant
o   Enhanced Master Mode PCI IDE Controller
    - Dual channel master mode PCI supports four Enhanced IDE devices
    - Mode 4 and Mode 5 transfer rate up to 22MB/sec
    - Sixteen doubleword of prefetch and write buffers
    - Interlaced commands between two channels
    - Separate IDE data bus and control signals from the PCI and ISA 
      bus to reduce loading and to enhance performance
    - Bus master programming interface for ATA controllers SFF-8038 
      rev.1.0 compliant
    - Full scatter and gather capability
    - Support ATAPI compliant devices
    - Support PCI native and ATA compatibility modes
    - Complete software driver support
o   Plug and Play Controller
    - Dual interrupt and DMA signal steering with plug and play control
    - Two programmable chip selects
    - Microsoft Windows 95TM and plug and play BIOS compliant
o   Sophisticated Power Management Unit
    - Normal, doze, sleep, suspend and conserve modes
    - System event monitoring with two event classes
    - One idle timer, one peripheral timer and one general purpose 
      timer
    - More than ten general purpose Input/Output ports
    - Six external event input ports with programmable SMI condition
    - Complete leakage control when external component is in power off 
      state
    - Primary and secondary interrupt differentiation for individual 
      channels
    - Clock stretching, clock throttling and clock stop control
    - Multiple internal and external SMI sources for flexible power 
      management models
    - APM 1.1 compliant
o   Synchronous ISA Bus Controller
    - Synchronous ISA bus clock
    - Programmable wait state, command delay and IO recovery time
    - Bus conversion and data alignment
    - Hardware and software de-turbo control
    - Fast reset and Gate A20 operation
    - Integrated 82C206 peripheral controller
    - Edge trigger or level sensitive interrupt
    - Flash EPROM and combined BIOS support
o   Built-in nand-tree pin scan test capability
o   0.6um mixed voltage, high speed and low power CMOS process
o   208 pin PQFP for VT82C575M
o   208 pin PQFP for VT82C576M
o   100 pin PQFP for VT82C577M
o   100 pin PQFP for VT82C416

**VT82C580VP   Apollo VP,  Pentium/M1/K5 PCI/ISA System      <02/15/96...
**VT82C580VPX  Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590     Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT  Apollo VP3, Single-Chip for Pentium with AGP  <10/03/97...
**VT82C598MVP  Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501       Apollo MVP4,Single-Chip 66-100MHz & AGP       <11/04/98...
**VT82C680     Apollo P6, Pentium-Pro Chip Set               <08/30/96...
**Support chips:
**VT82C505     Pentium/486 VL to PCI Bridge                  <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller          <10/13/96...
**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...