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**Cant find a chip?...
**Why this document is not GPL or a wiki...
**Definition of a chip set:...
**'chip set', 'chip-set' or 'chipset'?...
**What's not included:...
**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
**IBM PC/XT/AT...
*ACC Micro...
**Notes:...
**ACC82010 AT Chip Set (286 12.5/16MHz Max) c88...
**ACC82020 Turbo PC/AT Chip Set (286/386SX 25MHz Max) c88...
**ACC82021 Turbo PC/AT Chip Set (286/386SX 25MHz Max) >88...
**ACC82300 386 AT Chip Set (386DX) c88...
**ACC82C100 Single-Chip PC/XT Systems-Controller c90...
**ACC83000 Model 30 Integrated Chip Set (MCA) c88...
**ACC85000/A Model 50/60 Chipset (MCA) c88...
**ACC1000 Turbo PC/XT Integrated Bus and Peripheral Ctrl. 04/02/88...
**ACC2036 Single Chip Solution 2036 (286/386SX) <Jul92...
**ACC2046/ST 486DX/486SX/386DX Single Chip AT <Jul92...
**ACC2048 WB 486 Notebook/Embedded Single Chip [no datasheet] ?...
**ACC2051/NT PCI Single Chip Solution for Notebook Applications c96...
**ACC2056 ?Pentium 3.3V Notebook [no datasheet]<Jan96...
**ACC2057 PCI Notebook/Embedded Single Chip [no datasheet]<Aug96...
**ACC2066NT 486 Notebook/Embedded Single Chip [no datasheet] ?...
**ACC2086 486 VL-based System Super Chip Soluti[no datasheet] ?...
**ACC2087 Enhanced Super Chip (486 Single Chip) <Aug96...
**ACC2089 486 PCI-based System Super Chip [no datasheet] ?...
**ACC2168/GT 32-bit 486 Green System Single Chip [no datasheet] ?...
**ACC2178A 32-bit 486 Green System Single Chip [no datasheet] ?...
**ACC2268 ?486 [no datasheet] ?...
**ACC???? Maple/Maple-133 486-System-On-Chip [no datasheet] ?...
**
**Support Chips:
**ACC2016 Buffer and MUX Logic c96...
**ACC2020 Power Management Chip c92...
**ACC5500 Multifunction I/O Control Chip for PS2 Model 50/60 c88...
**
**Other chips...
*ALD...
**Notes:...
**Chips with no datasheet:...
**93C488 5x86/486 Single Chip PCI controller <Aug96...
*ALi...
**Notes:...
**M1207 286 Single Chip [no datasheet] ?...
**M1217/M1209 386SX/SLC Single Chip (40MHz) [no datasheet] c91...
**M1219 386DX/486 ISA Cache? Single Chip [no datasheet] ?
**M1419 386DX/486 ISA Cache Single Chip [no datasheet] c91
**Ml429/31/35 486 VLB/PCI/ISA [no datasheet, some info] cOct93...
**M1439/31/45 486 VLB/PCI/ISA [no datasheet, some info] <May95
***Notes:...
***Configurations:...
**M1489/87 FinALi-486 PCI Chipset <Feb95...
***Info:...
***Configurations:...
***Features:...
**M???? Genie, Quad Pentium [no datasheet, some info] c95...
***Notes:...
**M1451/49 Aladdin (Pentium) [no datasheet] ?...
***Configurations:...
**M1511/12/13 Aladdin II (Pentium) [no datasheet, some info] >Apr95...
***Notes:...
***Configurations:...
**M1521/23 Aladdin III 50-66MHz <Nov96...
***Info:...
***Configurations:...
***Features:...
**M1531/33/43 Aladdin IV & IV+ 50-83.3MHz <05/28/97...
***Info:...
***Configurations:...
***Features:...
**M1541/42/33/43 Aladdin V & V+ 50-100MHz ?...
***Info:...
***Configurations:
M1541/M1542 System Controller
M1533/M1543 PCI-to-ISA Bus Bridge
M1541 + M1533
M1541 + M1543
M1542 + M1533
M1542 + M1543
See the M1531 section for details on the M1533.
The datasheet is very confusing as it does not state how the terms
M1531, M1532, Aladdin V and Aladdin V+ relate to each other. According
to:
http://pclinks.xtreemhost.com/chipsets_pentium.htm
The Aladdin V and Aladdin V+ names are both associated with the M1541.
The M1541 has 5 revisions, A thru E. The M1542 part number is assoc-
iated with revision F onwards. The main difference with the M1542 is
that it now can cache 512MB of RAM, instead of only 128MB. The diff-
erence between the Aladdin V and Aladdin V+ is that the V+ officially
supports a 100 MHz bus, the V only 83.3 MHz.
However, none of this information can be derived from the datasheets
used to write the info and features section.
***Features:...
**M1561/43/35D Aladdin 7 ArtX [no datasheet, some info] 11/08/99
***Notes:...
***Info & Features:...
***Configurations:...
**M6117 386SX Single Chip PC <97...
***Notes:...
***Info:...
***Versions:...
***Features:...
**
**Support Chips:
**M1535/D South Bridge ?...
***Info:...
***Versions:...
***Features:...
**
**May not exist:...
**Later Chipsets:...
***PII
None of this information has been checked against actual datasheets.
North/South Name: CPU FSB AGP RAM
M1621/M1533 Aladdin Pro PII 66/100 2x 2GB EDO SDRAM
M1621/M1543/C Aladdin Pro II PII Dual 66/100 2x 2GB EDO SDRAM
M1631/M1535D Aladdin TNT2 (UMA) PIII/Cel 66/100 2x 1.5GB EDO SDRAM
M1632 Aladdin Cyber Blade 2 PIII 100 2x 1.5GB EDO SDRAM
M1641B/M1535D Aladdin Pro 4 PIII/Cel 66/100 4x 1.5GB EDO SDRAM
M1644/M1535D+ Aladdin Cyberblade XT PIII/Cel 100/133 4x 3GB SDRAM DDD
M1644M/M1535D+ Aladdin-T Cyberblade [same as 1644/M1535D+ but supports Tualatin]
M1651/M1535D+ Aladdin Pro 5 PIII/Cel 100/133 4x 3GB SDRAM DDR
M1651T/M1535D+ Aladdin Pro 5T [same as M1651/M1535D+ but supports Tualatin]
"Aladdin Cyberblade" above is short for "CyberAladdin Cyberblade". All
Cyberblade chips have integrated video, as does the Aladdin TNT2.
***Athlon...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
**AMD Am286ZX/LX (286 Embeded CPU + integrated peripherals) ?
**AMD Elan Series (386/486 Embeded CPU + integrated peripherals) ?
**AMD 640/645 (Pentium Based on VIA VT82C590) [some info] c97...
**Later Chipsets:...
*Chips & Technologies...
**CS8220 PC/AT compatible CHIPSet (82C201/C202/A203/A204/A205)cOct85...
**CS8221 NEW Enhanced AT (NEAT) (82C211/82C212/82C215/82C206) c86...
**CS8223 LeAPset [no datasheet] ?
**CS8225 CHIPS/250 PS/2 50/60 [no datasheet, some info] c88...
**CS8227 CHIPSlite (82C235/82C641) ?...
**CS8230 386/AT (82C301/302/303/304/305/306)cFeb87...
**CS8231 TURBO CACHE-BASED 386/AT (82C301/307/303/304/305/306) c86
***Info:...
***Configurations:...
***Features:...
**CS8232 CMOS 386/AT (82C301/302/303/304/305/306) c86...
**CS8233 PEAK/386 AT (Cached) (82C311/82C315/82C316) c:Dec90...
**CS8236 386/AT (82C301/2/3/4/5/6/206) c86...
**CS8237 TURBO CACHE-BASED 386/AT (82C301/7/3/4/5/6/206) c86...
**CS8238 CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226) c:Aug89...
**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90
assumed to be sx variant of of ELEAT
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88
***Info:...
***Versions:...
***Features:
o Single Chip UART and Analog Data Separator
o 100% functionally compatible to the IBM PS/2 model 50, 60, and 80
o Fully compatible NSl6550 Asynchronous Communications Element
o 16 bytes FIFO for transmitter and receiver buffers
o Easy interface to the Industry standard floppy disk controllers
(765A/765B/8272A)
o Supports multiple data rates (250K, 300K, and 500Kbps)
o High drive, 48 mA output buffer
o Schmitt trigger inputs
o Low power advanced CMOS technology
o 68 pin PLCC or 80 pin Flat Pack
**82C710 Universal Peripheral Controller c:Aug90
***Info:...
***Versions:
82C710
***Features:...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93
***Info:...
***Versions:...
***Features:...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
**82C591/2 3/486 <Mar92...
**82C593 3/486 [no datasheet] <May92...
**82C596/A 3/486 Writeback Cache [no datasheet] <11/11/92...
**?????? 486 EISA chipset [no datasheet] <Feb93...
**82C599 PCI-VLB Bridge [no datasheet, some info] ?...
**82C693 PCI-ISA Bridge [no datasheet] ?...
*Efar Microsystems [no datasheets, some info]...
**EFAR-8290WB 386/486 Writeback PC/AT Chipset [no datasheet] ?...
**82EC798 386/486 Writeback PC/AT Single Chip [no datasheet] ?
**Other:...
*ETEQ...
**?????? "Cougar/Bobcat" 386DX/486DX chipset [no datasheet] cNov91...
**?????? "Bengal" 386DX/486 (WriteBack) [no datasheet] cNov91...
**ET2000 386/486 WB Chipset ?...
**ET6000 "Cheetah" 486DX/SX Non-Cache System <Apr92...
**ET9000 "Jaguar" 486 Write Back Cache AT Single Chip <Jun92...
**ET9800/391 "Firefox" 386SX Write Back chipset [no datasheet] ?...
**82C390SX "Panda" S.C. 386SX Direct Mapped Cache [no d.sheet]cFeb92...
**66x8 VIA clones [no datasheet] ?
***Notes:...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel
**IBM PC/XT/AT Chip Sets...
**82230/82231 High Integration AT-Compatible Chip Set(ZyMOS) c:Aug88...
**82310 Micro Channel Compatible Peripheral Chip Set 04/21/88...
**82311 High Integration MCA Compatible Perip. Chip Set 11/14/88...
**82320 MCA compatible Chipset [no datasheet] 04/10/89...
**82340DX Chip Set (VLSI) (82346/82345/82355) 01/08/90...
**82340SX Chip Set (VLSI) (82343/82344) 01/25/89...
**82350 EISA Chip Set 07/10/89...
**82350DT EISA Chip Set 04/22/91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82420TX/ZX PCIset (for 486) TX (Saturn), ZX (Saturn II) c:Nov92...
***Notes:...
***Info:...
***Versions:...
***Configurations:...
***Features:...
**82420EX PCIset (for 486) EX (Aries) (82425EX/82426EX) <Dec94...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82430LX PCIset (Pentium) LX (Mercury) (82433LX/82434LX) 03/22/93...
***Notes:...
***Info:...
***Configurations:
Parts:
Intel 82434LX (PCMC) PCI/CACHE/MEMORY CONTROLLER
Intel 82433LX (LBX) LOCAL BUS ACCELERATOR
ISA:
82434LX + 2x 82433LX + 82378IB
82434LX + 2x 82433LX + 82378ZB
The main difference between the 82378IB and 82378ZB is the number of
PCI masters supported. See the 82378 section for details.
EISA:
Intel 82434LX + 2x 82433LX + 82374EB + 82375EB
Intel 82434LX + 2x 82433LX + 82374SB + 82375SB
The main difference between the EB and SB variants is that the SB
includes power management options. It was released later when
various enhancements had been made to the EB variant. See the
82374/82375 section for details. It is unlikely the SB variant is
paired with this chipset as it was released when the 430LX was being
replaced with the 430NX.
These chipsets are often paired with the SMC 665 for I/O support or
the NCR 810 for SCSI.
Why this section is so detailed:
Any chips manufactured before Jan 94 have serious problems with the
PCI/EISA bridge's throughput. The problem affects the ISA version too,
but is less pronounced.
Two references from November'93 give some inportant detail that seems
to be missed in the datasheets. It would appear there is an update to
the 82374/82375EB EISA components in late '93, that has some
significant changes. these are not reflected in the datasheets
referenced.
It would appear the mentioned redesign, maps well to the update of
82378 ISA component from the 82378IB to the 82378ZB. Though no
information specifically stating this has been found. It is only that
these are in the same time period.
****References:...
***Features:...
**82430NX PCIset (Pentium) NX (Neptune) (82433NX/82434NX) Mar94...
**82430FX PCIset (Pentium) FX (Triton I) (82437FX/82438FX)01/31/95...
**82430MX PCIset (Pentium) MX (Mobile Triton)(82437/438MX)11/01/95...
**82430HX PCIset (Pentium) HX (Triton II) (82439HX) 02/12/96...
**82430VX PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96...
**82430TX PCIset (Pentium) TX (Triton II) (82439TX) 02/17/97...
**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95
***Notes:...
***Info:
****General:...
****82454KX/GX PCI Bridge (PB):
The 82454KX/GX PB are single-chip PC-compatible host-to-PCI bridges. A
rich set of Host-to-PCI and PCI-to-Host bus transaction translations
optimize bus bandwidth and improve system performance. All ISA and
EISA regions are supported. Three programmable memory gaps can be
created—a PCI Frame Buffer Region and two general-purpose memory gaps
(the Memory Gap Region and the High Memory Gap Region). The PB has a
synchronous interface to the Pentium Pro processor bus and supports a
derived clock for the synchronous PCI interface. The PB generates and
checks ECC over the host data bus (82545GX only), and generates and
checks parity over the address and request/response signal lines (both
82454KX and 82454GX). The PB also checks address and data parity on
the PCI bus. For the 82454GX, two PBs can be used in a system.
The Intel 450KX/GX PCIsets may contain design defects or errors known
as errata. Current characterized errata are available upon request.
3.0 PB FUNCTIONAL DESCRIPTION
This section describes the PB functions and hardware interfaces
including the I/O and Memory Map, Host bus, PCI bus, and Dual-bridge
Architectures. Data Integrity and Error Handling are covered. Clock,
Reset, and PB configuration are also covered.
3.1 Memory and I/O Map
The 82454KX/GX PB provides the interface between the host bus and the
PCI bus. Memory transactions can be sent from the PCI bus to the host
bus and from the host bus to the PCI bus. Gaps and positive decode
ranges can be programmed via the configuration registers. For the
82454KX, I/O transactions can be sent from the host bus to the PCI
bus. However, I/O transactions can not be sent from the PCI bus to the
host bus.
----------------------------------------------------------------------
For the 82454GX, both memory and I/O transactions can be sent from
the PCI bus to the host bus and from the host bus to the PCI
bus. Memory and I/O gaps and positive decode ranges can be
programmed via the configuration registers.
----------------------------------------------------------------------
If an access is enabled to be forwarded from the host bus to the PCI
bus, the corresponding access on the PCI bus is ignored (not forwarded
to the host bus). Conversely, if an access is enabled to be forwarded
from the PCI bus to the host bus, the corresponding access on the host
bus is ignored (not forwarded to the PCI bus).
The PB and MC perform a positive address decode of each host
transaction and one default device handles the unclaimed
transactions. In a standard PC system, unclaimed transactions are sent
to the ISA bus. Thus, the PB (Compatibility PB in an 82454GX dual PB
system) is the default responder on the host bus.
3.1.1 MEMORY ADDRESS MAP [see datasheet]
3.1.2 I/O ADDRESS MAP [see datasheet]
3.2 Host Bus Interface
The Pentium Pro processor bus provides an efficient, reliable
interconnect between multiple Pentium Pro processors and the PB and
MC. The bus provides 36 bits of address, 64 bits of data, protection
signals needed to support data integrity, and the control signals to
maintain a coherent shared memory in the presence of multiple caches.
The Pentium Pro processor bus achieves high bus efficiency by
providing support for multiple, pipelined transactions and deferred
replies. A single Pentium Pro processor may have up to four
transactions outstanding at the same time, and can be configured to
support a total of either one or eight transactions active on the
Pentium Pro processor bus at any one time. The PB supports up to eight
active transactions on the host bus (In-Order Queue depth of
8). During the host bus reset and configuration, all host bus devices
are configured to support either one or eight transactions in their
In-Order Queue.
The number of transactions that can target a particular bus client is
configured separately from the total number of transactions allowed on
the bus. The PB accepts up to four transactions into the Outbound
Request Queue that target its associated PCI bus.
The PB provides four 32-byte buffers for outbound data (host-to-PCI
writes or PCI reads from the host bus), and four 32-byte buffers for
inbound data (PCI-to-host writes or CPU reads from PCI).
As a host bus master, the PB does not support deferred responses. The
EXF1# extended function signal (Defer Enable) will never be asserted
for a host transaction initiated by the PB.
The host bus supports ECC over the data bus, and parity protection
over the address, request, and response lines. The PB generates and
checks ECC over the data lines (82454GX only), and generates and
checks parity over the address and request/response signal lines (both
82454KX/GX). Note, ECC generation and checking on the data lines and
parity generation and checking on the request/response lines can be
enabled or disabled during system configuration.
3.3 PCI Bus Interface
The PB has a standard master/slave PCI bus interface. All legal PCI
(PCI specification 2.0) bus transactions are supported. PCI cycle
termination and error logging/reporting are discussed in the Data
Integrity and Error Handling section. The PCI arbitration unit is not
implemented in the PB.
PCI Locks. Systems which support PCI initiate locks (either inbound
locks or peer-to-peer) must configure the arbiter for full bus locks
rather than resource locks. The PB will not recognize resource locks
made by peer-to-peer accesses. When a PCI master asserts LOCK# while
targeting the PB, the locked PCI transactions are converted to locked
host bus transactions. The host bus lock continues as long as the PCI
master asserts LOCK# for exclusive access to the PB. The host bus lock
is assisted by the bridge continuing to assert BPRI# as long as the
PCI bus is asserting resource lock to the bridge. Additional locked
CPU transactions are issued if the PCI master continues to burst.
In systems in which target abort reporting is disabled, the write
portion of a lock will be committed even when the read portion is
aborted.
Host Bus Locks. Any transactions that target the bridge during a host
bus lock are converted into a similar PCI lock transaction. The lock
on the PCI bus is held until the host bus lock is released. Locks
over the Frame Buffer region can be disabled through a mode bit in the
PCI Frame Buffer Range Register.
Indivisible Operations. CPU initiated read operations that cross a
Dword boundary (e.g., Read 8 Bytes, Read 16 Bytes, etc.) are
indivisible operations on the host bus. However, since the PCI
protocol allows a target device to disconnect at any point in a
transfer sequence, these operations must be locked indivisible on the
PCI bus. The PB optionally locks all CPU initiated reads that cross a
Dword boundary. This mode is enabled by setting the Lock Atomic Reads
in the PB Configuration Register. CPU initiated Write operations
(e.g., Write 8 Bytes, Write 16 Bytes, etc.) are indivisible operations
on the host bus. However, these accesses can not be made indivisible
on the PCI bus because the PCI Specification states that the first
transaction of a locked operation must be a read. Therefore, software
must not rely upon the atomicity of CPU initiated write transactions
greater then 32 bits once they are translated to the PCI bus.
Software Generated Special Cycles. This optional feature is not
supported by the 450KX/GX PCIset.
3.4 Data Integrity and Error Handling
Several data integrity features are included in the PB. These include
ECC on the host data bus (450GX only), parity on the host address,
parity on the CPU Request/Response signals, and parity on the PCI
bus. Error logging (setting a status bit) and reporting (generating an
error signal) are controlled by the PCICMD Register (04–05h), PCISTS
Register (06–07h), ERRCMD Register (70h), ERRSTS Register (71h),
EXERRCMD Register (C0–C3h), and EXERRSTS Register (C4–C7h).
3.4.1 HOST BUS ERRORS [see datasheet]
3.4.2 PCI BUS ERRORS [see datasheet]
3.5 Dual PB Architectures (82454GX Only)
----------------------------------------------------------------------
In a dual bridge system, one PB is configured as the default bridge
(Compatibility PB) after power-on RESET. The Compatibility PB
provides a path to the ISA bus devices needed in a PC-compatible
system such as the boot ROM. The Compatibility PB is the highest
priority bridge in a dual bridge system to ensure a fast enough
response time for ISA bus masters. See the Clocks, Reset, and
Configuration section for details on configuring a PB as the
Compatibility PB.
Multiple I/O APICs
In a dual PB system, the auxiliary PCI bus interrupt requests are
routed to the auxiliary bus I/O APIC. When booting the system with
one processor, the IRQ control logic is enabled, feeding the
interrupt request to the standard interrupt controller in the
ESC. When the system is in multiprocessor mode, the routing logic is
disabled after ensuring PB buffer coherency, and interrupt requests
are forwarded to the processors via the APIC bus. The Intel 82379AB
(SIO.A) may be utilized as a stand-alone I/O APIC device. However,
the additional logic for interrupt/memory consistency and the
interrupt steering logic is not provided in the SIO.A and must be
implemented externally.
Dual Bridge Arbitration for the Host Address Bus
The PB requests the host address bus with BPRI#. However, only one
bridge is allowed to drive BPRI# at a time. With two PBs, an
internal arbiter is used to establish bus ownership. This
arbitration is transparent to the CPU and other symmetric bus
agents.
In a two PB system, the compatibility PB acts as the arbitration
unit between it and the other PB, as shown in Figure 6 [see
datasheet]. When a PB is programmed to be the arbitration unit, its
IOGNT# is the input for the IOREQ# from the other bridge and IOREQ#
is the output to IOGNT# of the other bridge.
Figure 7 [see datasheet] shows the minimum arbitration timing in a
two bridge system. IOGNT# may assert later than shown and IOREQ# may
negate later than the two clocks after IOGNT# negates.
The arbiter bridge can assert BPRI# as long as it has not asserted
its IOREQ# (Grant to the other bridge) and BPRI# is not currently
driven. In turn, the other bridge, after receiving it’s IOGNT#,
samples BPRI# released before assuming ownership of BPRI#. This
allows the BPRI# arbitration to be performed in parallel with
another bridge transfer. This timing is shown in Figure 8. [see
datasheet]
Bridge-to-bridge misaligned (split) locks are not recommended and
could cause deadlock in systems.
Bridge-to-Bridge Communication
PB-to-PB communication is supported by the PB, but is not recom-
mended for optimal performance.
PB-to-PB transactions involving a standard bus bridge (SIO,
PCEB/ESC) require special precautions to avoid deadlock and latency
problems. The PB does NOT support PB-to-PB transactions from agents
that cannot be backed off such as those originating on an ISA or
EISA bus and targeting a device on a different PB’s PCI bus. Any
device that asserts FLSHBUF# must be targeting a device on the local
PCI bus or the host bus.
Dual PB Configuration (82454GX only)
During a power-on reset (PWRGD asserted), IOREQ# and IOGNT# provide
a unique identification number for each PB (PBID). The PBID is part
of the PB’s PCI Bridge Device Number and is available to programmers
via the BDNUM Register (offset 49h). The Dual PB system must have a
pull-up and a pull-down as shown in Figure 9. The encoding for these
signals is shown in Table 10. [see datasheet]
----------------------------------------------------------------------
3.6 Peripheral Operation and Performance
The 82454 PB is designed for optimum processor performance to get the
most out of a Pentium Pro processor’s capabilities. In systems with
multiple PCI devices, one must take into account the architecture of
the 82454 PB in order to maximize overall system performance.
3.6.1 MATCHING PERIPHERALS TO THE 450KX/GX [see datasheet]
3.6.2 DISTRIBUTING PERIPHERALS WITHIN THE I/O SUBSYSTEM
While this is not necessary for system operation, systems implementing
dual 82454 PBs have additional latitude to isolate high speed I/O
devices from competing system traffic initiated by the CPU.
All graphics and the vast majority of I/O space communication (such as
keyboard controller, system timer, and interrupt support) will be
directed to the primary PCI bus behind the Compatibility 82454
PB. (This is the bus with a subsequent connection via another bridge
to an ISA or EISA bus.) This processor traffic will compete with bus
mastering peripheral devices attempting to move data to and from
system memory. It is desirable then to place latency sensitive devices
behind the Auxiliary 82454 PB, to isolate them from competing CPU
traffic.
In a full system configuration, in which all PCI slots are occupied,
it is preferable to segregate peripherals intelligently. Limit the
primary PCI bus to graphics accelerators and SCSI RAID controllers,
leaving Auxiliary 82454 PB PCI slots free for latency-sensitive
devices such as network adapters. In systems connecting a large number
of network adapters, divide them evenly between the two busses to
minimize the amount of latency-sensitive competition at any one point
in the system.
3.6.3 PCI-TO-PCI BRIDGES [see datasheet]
3.6.4 BIOS PERFORMANCE TUNING [see datasheet]
3.7 Clock, Reset, and Configuration
3.7.1 SYSTEM CLOCKING [see datasheet]
3.7.2 SYSTEM RESET [see datasheet]
3.7.3 SYSTEM INITIALIZATION [see datasheet]
3.7.5 USING THE 82379AB SIO.A PCI-TO-ISA BRIDGE WITH THE 450KX/GX
There is an anomaly with systems that use the 82379AB (SIO.A) during
targeted PCI Resets. In addition, 450GX/KX systems can boot improperly
at power-up and react improperly to the assertion of the Pentium Pro
bus signal BINIT# signal (due to the assertion of PCIRST# via BINIT#).
The SIO.A drives SMI#, ALT_A20, INT, NMI, IGNNE#, ALT_RST#, and
STPCLK# low while PCIRST# is asserted low, and does not drive them
high until after PCI reset is released. An anomaly can exist with
these seven signals remaining low during and immediately after PCIRST#
is negated. The three instances in which this can cause an anomaly
are: during a targeted PCI Reset, and in a 450GX/KX-Pentium Pro
processor system, both during power-up and when BINIT# is asserted on
the Pentium Pro processor bus.
....[see datasheet]
3.8 Host to PCI Bus Command Translation [see datasheet]
3.9 PCI to Host Bus Command Translation [see datasheet]
****Memory Controller (MC) 82453KX/GX (DC), 82452KX/GX (DP), 82451KX/GX (MIC)...
***Configurations:...
***Features:...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
**8289 Bus Arbiter (808x) c79...
**82289 Bus Arbiter for iAPX 286 Processor Family c83
***Info:...
***Info:...
***Versions:...
***Features:...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
***Notes:...
***Info:...
***Versions...
***Features:...
**82335 High-Integration Interface Device For 386SX c:Nov88...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82360SL I/O Subsystem 10/05/90...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
***Notes:...
***Info:...
***Versions:...
***Configurations:
82374EB + 82375EB (c93)
82374SB + 82375SB (c94)
***Features:...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
***Notes:...
***Info:...
***Configurations:...
***Features:
o High Performance Second Level Cache
- Zero Wait States at 66 MHz
- Two-Way Set Associative
- Writeback with MESI Protocol
- Concurrent CPU Bus and Memory Bus Operation
- Boundary Scan
o Pentium Processor (735\90, 815\100)
- Chip Set Version of Pentium Processor (735\90, 815\100)
- Superscalar Architecture
- Enhanced Floating Point
- On-Chip 8K Code and 8K Data Caches
- See Pentium Processor Family Data Book for More Information
o Highly Flexible
- 1 Mbyte to 2 Mbyte
- 64-, or 128-Bit Wide Memory Bus
- Synchronous, Asynchronous and Strobed Memory Bus Operation
- Selectable Bus Widths, Line Sizes, Transfers and Burst Orders
o Full Multiprocessing Support
- Concurrent CPU, Memory Bus and Snoop Operations
- Complete MESI Protocol
- Internal/External Parity Generation/Checking
- Supports Read For Ownership, Write-Allocation and Cache-to-Cache
Transfers
**
**Later chipsets (basic spec):
**440 series:...
***440FX (Natoma) 05/06/96...
***440LX (Balboa) 08/27/97...
***440BX (Seattle) c:Apr'98...
***440DX (?) c:?...
***440EX (?) c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?) 05/17/99...
***440MX (Banister) 05/17/99...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01
Chips:
[82815P] (MCH) [82801AA] (ICH) [82802] (FWH)
CPUs: P-III/P-III(T)*1/Celeron
DRAM Types: SDRAM PC133
Mem Rows: 6
DRAM Density: 64Mbit 128Mbit 256Mbit
Max Mem: 512MB
ECC/Parity: No
AGP speed: 1x 2x 4x
Bus Speed: 66 100 133
PCI Clock/Bus: 1/2 1/3 1/4 PCI 2.2
>*1 P-III Tualatin first supported from B-0 stepping of chipset.
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
**Notes:...
**GC101/102 12/16MHz PC/AT Compatible Chip Set c:Feb88...
***Info:...
***Configurations:...
***Features:...
**GC101/102/103 12/16MHz PC/AT Compatible Chip Set + EMS 4.0 c:Jul89...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**GCK113 80386 AT Compatible Chip Set c:oct89...
***Info:...
***Configurations:...
***Features:...
**GCK181 Universal PS/2 Chip Set c:Mar89...
***Info:...
***Configurations:...
***Features:...
**HT11 Single 286 AT Chip [no datasheet] <Aug90...
***Notes:...
**HT12/+/A Single 286 AT Chip with EMS support c:Aug90...
***Info:...
***Configurations:...
***Features:...
**HT18 80386SX Single Chip c:Sep91...
***Info:...
***Configurations:...
***Features:...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
***Info:...
***Configurations:...
***Features:...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
***Info:...
***Configurations:...
***Features:...
**HT25 3-volt Core Logic for 386SX c:Dec92...
***Info:...
***Configurations:...
***Features:...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
***Notes:...
**HTK320 386DX Chip Set c:Sep91...
***Info:...
***Configurations:...
***Features:...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
***Notes:...
***Info:...
***Configurations:...
***Features:
o Support for 486SX/DX/DX2 CPU
o 2 - 184 pin PQFP devices
o Local bus interface
o 16, 20, 25 and 33MHz CPU speeds
o Fully static operation
o Weitek 4167 supported
o System and Video BIOS on single ROM
o Uses 0.7 Micron HCMOS process
ISA Controller
o AT Compatible
o Synchronized 8MHz ISA bus
o Posted backplane memory writes
o 10 or 16 bit l/O mapping
o Integrated 82375, 82593 and 8254 functionality
o Fast gate A20/Fast reset
Write Buffer
o 4 deep on-chip buffer
o Byte gathering
o Out of order operation
o Full or partial write buffer hits
DRAM Controller
o Line burst capability from DRAM to 80486
o 256K/1M/4M/16M DRAMs
o Mixed memory types
o EMS 4.0
o Hidden refresh operation
o 256MB Maximum system memory
o Staggered refresh
o Shadowing in 16KB increments between 640KB and 1MB
o Remapping
o Fast paging
o 2 or 4 way interleaving
**Support Chips:
**HT44 Secondary Cache c:Jun92...
***Info:...
***Versions:...
***Features:...
**Other:...
*HMC (Hulon Microelectronics)...
**HMC82C206 Integrated Peripherals Controller (10MHz C&T 82c206) ?...
***Info:...
***Versions:...
***Features...
*Logicstar...
**SL600X PC / AT Compatible Chipset (10/12MHz) <Jul87...
***Info:...
***Configurations:...
***Features:...
**Support Chips:
**SL6012 Memory Mapper for PC-AT (74LS612 compatible) <Jul87...
***Info:
The SL6012 Memory Mapper is intended for use in PC-AT design. It can
expand an address bus by 4 bits. In PC-AT applications, 4 bits of the
source address are used to select 1 of 16, eight bit map
registers. These registers are normally programmed (through software)
with the starting address of each memory page. The register data is
output directly for use as the most significant bits of the expanded
address bus. The 8 bits from the SL6012 are used along with the unused
source address bits to form the expanded address bus.
As shown in Table 1 [see datasheet], the SL6012 has three modes of
operation; read, write and map. Data may be written into, or read from
the Memory Mapper when chip select CSN is low. The register select
inputs (RS0 through RS3) select one of the sixteen map registers. When
RWN is low, data is written into a register from the data bus. When
RWN is high data is output from a Memory Mapper register to the data
bus.
The map mode of operation is selected when chip select CSN is high. In
this mode, the register data selected by the map address inputs (MA0
through MA3) will be available on the map outputs (MO0 through
MO7). Note that the map registers are addressed by either the RS
inputs or the MA inputs depending upon the operating mode. When MEN
(Map Enable) is low the map outputs (MO0-MO7) are active. When MEN is
high, the map outputs are at high impedance.
***Versions:...
***Features:...
**SL9010 System Controller (80286/80386SX/DX, 16/20/25MHz) <oct88...
**SL9020 Data Controller <oct88...
**SL9025 Address Controller <oct88...
**SL9090 Universal PC/AT Clock Chip <oct88
***Info:...
***Versions:...
***Features:...
**SL9250 Page Mode Memory Controller (16/20MHz 8MB Max) <oct88
***Info:...
***Versions:...
***Features:...
**SL9350 Page Mode Memory Controller (16/20/25MHz 16MB Max) <oct88...
**Other:...
*Motorola...
**IBM AT: MC146818 Real Time Clock <84...
*OPTi...
**82C263 SCNB Single Chip Notebook c:92...
**82C281/282 Cache Sx/AT (386SX) <08/22/91...
**82C283 386SX System Controller c:91...
**82C291 SXWB PC/AT Chipset (386SX) c:91...
**82C295 SLCWB PC/AT Chipset (386SX) ?...
**82C381/382 HiD/386 (386DX) c:89...
**82C391/392 386WB PC/AT Chipset (386DX) <Dec90...
**82C461/462 Notebook PC/AT chipset [no datasheet] ?...
**82c463 SCNB Single Ship Notebook c:92...
**82c465MV/A/B Single-Chip Mixed Voltage Notebook Solution <Oct97...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
**Other alias:...
**Notes:...
**Early Chipsets:...
**Later Chipsets:...
*SIS...
**85C211/2/5 286 chipset [no datasheet] ?...
**85C310/320/330 'Rabbit' High performance 386DX chipset <91...
**85C360 ISA 386DX Single Chip chipset [no datasheet] ?
***Notes:...
**85C401/402 ISA 486DX/SX Cache chipset [no datasheet] ?...
**85C406/5/411/420/431 EISA 386/486 Chipset [no datasheet] c91...
**85C460 ISA 386DX/486 Single Chip [no datasheet] ?
**85C461 ISA 386DX/486 Single Chip [no datasheet] ?...
**85C471/407 Green PC ISA-VLB 486 Single Chip <94
***Info:...
***Configurations:...
***Features:...
**85C496/497 486-VIP 486 Green PC VESA/ISA/PCI Chipset <95
***Info:
The SiS 486-VIP (VESA/ISA/PCI) chips are two-chip solution ideally for
Intel's 80486, SL Enhanced 486, P24D/P24T/DX4 CPU, AMD's 486, Enhanced
Am486 and Cyrix's Cx486 (M7)/Cx 5x86 CPU based on green AT system. By
supporting the most popular industrial standard system interfaces, it
provides flexible configurations for system design and applications.
The SiS85C496 PCI & CPU Memory Controller (PCM) integrates the Host
Bridge (Host Interface), the cache and main memory DRAM Controller,
the PCI Bridge, the built-in IDE Controller, and the FS-Link Bus (Fast
Slow Link Bus). It provides the address paths and bus control for
transfers among the Host (CPU/L1 cache), main memory (L2 cache and
DRAM), the Peripheral Component Interconnect (PCI) Bus, and the
FS-Link Bus. The L2 cache controller supports both write-through and
write-back cache policies and cache sizes up to 1 MBytes. The cache
memory can be built using standard asynchronous SRAMs. The main
memory DRAM controller interfaces DRAM to the Host Bus, PCI Bus, and
FS-Link Bus. Up to eight single sided SIMMs or four double sided SIMMs
provide a maximum of 255 MBytes of main memory. The installation of
DRAM SIMMs is "Table-Free", which allows the SIMMs be installed into
any slot location and any combinations. The built-in IDE hard disk
controller allows CPU accessing hard disk and also provides higher
system integration with lower system cost. The 85C496 is intended to
be used with the SiS85C497 which is a AT Bus Controller with built-in
206 controller.
The SiS85C497 AT Bus Controller and Megacells (ATM) provides the
interface between PCI/CPU/Memory Bus (fast machine) and the ISA Bus
(slow machine). It also integrates many of the common I/O functions
in today's ISA based PC systems. The 85C497 comprises the FS-Link
interface (Fast-Slow Link interface), ISA bus controller , DMA
controller and data buffers to isolate the FS-Link Bus from the ISA
Bus and to enhance performance. It also integrates a 14 channel
edge/level interrupt controller, refresh controller, a 8-bit BIOS
timer, three programmable timer/counters, non-maskable-interrupt (NMI)
control logic, Power Management Unit, and RTC. Figure 1 .1 [see
datasheet] shows the system block diagram.
***Configurations:...
***Features:...
**85C501/502/503 Pentium/P54C PCI/ISA Chipset <01/09/95...
**5101/5102/5103 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5120 Pentium PCI/ISA Chipset (Mobile) <01/28/97
***Info:...
***Versions:...
***Features:...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset <04/02/95
***Info:...
***Configurations:...
***Features:...
**5511/5512/5513 Pentium PCI/ISA <06/14/95...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96
***Info:...
***Configurations:...
***Features:...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98
***Info:...
***Configurations:...
***Features:...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?
***Notes:...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
**SL82C360 'Haydn' 80386DX/SX chipset [no datasheet] c:Jun91...
**SL82C460 'Haydn II' 80486 chipset [no datasheet] c:Jun91...
**SL82C470 'Mozart' 486/386 EISA chipset c:Dec91...
**SL82C490 'Wagner' 486? [no datasheet] ?...
**SL82C550 'Rossini' Pentium [no datasheet] c:95...
**
**Support Chips:
**SL82C365 Cache Controller (for 386DX/SX) c:91...
**SL82C465 Cache Controller (for 486/386DX/SX) c:91...
*TI (Texas Instruments)...
**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers <84
***Notes:...
***Info:
Each 'LS610 and 'LS612 memory mapper integrated circuit contains a
4-line to 16-line decoder, a 16-word by 12-bit RAM, 16 channels of
2-line to 1-line multiplexers, and other miscellaneous circuitry on a
monolithic chip. Each 'LS610 also contains 12 latches with an enable
control.
The memory mappers are designed to expand a microprocessor's memory
addressing capability by eight bits. Four bits of the memory address
bus (see System Block Diagram)[see datasheet] can be used to select
one of 16 map registers that contain 12 bits each. these 12 bits are
presented to the system memory address bus through the map output
buffers along with the unused memory address bits from the CPU.
However, addressable memory space without reloading the map registers
is the same as would be available with the memory mapper left out.
The addressable memory space is increased only by periodically
reloading the map registers from the data bus. This configuration
lends itself to memory utilization of 16 pages of 2^(n-4) registers
each without reloading (n - number of address bits available from
CPU).
These devices have four modes of operation: read, write, map, and
pass. Data may be read from or loaded into the map register selected
by the register select inputs (RS0 thru RS3) under control of R/W
whenever chip select (CS) is low. The data I/O takes place on the data
bus DO thru D7. The map operation will output the contents of the map
register selected by the map address inputs (MA0 thru MA3) when CS is
high and MM (map mode control) is low. The 'LS612 output stages are
transparent in this mode, while the 'LS610 outputs may be transparent
or latched. When CS and MM are both high (pass mode), the address bits
on MA0 thru MA3 appear at M08-MO11, respectively (assuming appropriate
latch control) with low levels in the other bit positions on the map
outputs.
***Versions:...
***Features:...
**TACT82000 3-Chip 286 [no datasheet] c89...
**TACT82411 Snake Single-Chip AT Controller c90...
**TACT82S411 Snake+ Single-Chip AT Controller [no datasheet] c91...
**TACT83000 AT 'Tiger' Chip Set (386) c89...
**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91...
**Other:...
*UMC...
**UM82C*** (IBM/INTEL Direct replacement) c87...
**UM82C088 PC/XT Integration Chip <91...
**UM82C230 286AT MORTAR Chip Set <91...
**UM82C210 386SX/286 AT Chip Set <91...
**UM82C3xx Twinstar & UM82C336F/N & UM82C39x [no datasheet] ?...
**UM82C380 386 HEAT PC/AT Chip Set <91...
**UM82C480 386/486 PC Chip Set c91...
**UM82C493/491 ??????????????? [no datasheet] ?...
**UM8498/8496 486 VL Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886 HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890 Pentium chipset [no datasheet] ?...
**
**Support Chips:
**UM82152 Cache Controller (AUStek A38152 clone) <91
***Info:...
***Versions:...
***Features:...
**UM82C852 Multi I/O For XT <91...
***Info:...
***Versions:...
***Features:...
**UM82C206 Integrated Peripheral Controller <91...
***Info:...
***Versions:...
***Features:...
**UM82c45x Serial/Parallel chips ?...
***Notes:...
**Other chips:...
***Video:...
***Disk:...
***Peripheral:
UM2661 Enhanced Programmable Communications Interface (EPCI)
UM2681 Dual Asynchronous Receiver/Transmitter (DUART)
UM6520/A Peripheral Interface Adapter(PIA) (MC6820)
UM6521/A Peripheral Interface Adapter(PIA) (MC6821)
UM6522/A Versatile Interface Adapter (VIA)
UM6532/A RAM, I/O, Timer Array
UM6551 Asynchronous Communication Interface Adapter (ACIA)
UM82C01 Capacitance Keyboard Encoder (CKE)
UM82C11-C Printer Adapter Interface (PAI)
UM82C450 Asynchronous Communication Element (ACE)
UM82C451 Parallel/Asynchronous Communication Element
UM82C452 Single Chip Multi-I/O (Serial/Parallel)
UM82C550 Asynchronous Communications Element with FIFOs
UM82450 Asynchronous Communication Element (ACE)
UM8250A Asynchronous Communication Element (ACE)
UM8250B Asynchronous Communication Element (ACE)
UM82C8167 RTC
***Other:...
*Unresearched:...
**A - D...
***Appian Technology...
***Atmel...
***Biostar...
***Citygate...
***Cyrix...
***Other...
**E - G...
***Evergreen?...
***Other...
**H - I...
***Hint...
***Other...
**J - R...
***Micro Integration...
***Micron...
***Oak...
***Other:...
**S...
***Shasta...
***SARC...
***ServerWorks (Reliance Computer Corporation)...
***Sun Electronics (SUNTAC) ...
***Syslogic...
***Other
Summit chipset - 3/486
Samsung KS82C884
SOLUTIONS 88C211, 88C212, 88C215, P82C206 - isa 386sx c1990
ST Microelectronics PC Client ST86 processor
**T - Z...
***Toshiba ...
***UniChip ...
***USA...
***Other...
*VIA
**SL9XXX FlexSet family General information...
**SL9011 System Controller (80286/80386SX/DX, 16/20/25MHz) <Jan90...
**SL9020 Data Controller <Jan90...
**SL9025 Address Controller <Jan90...
**SL9030 Integrated Peripheral Controller <Jan90...
**SL9090/A Universal PC/AT Clock Chip <oct88...
**SL9095 Power Management Unit ?
***Info:...
***Versions:...
***Features:...
**SL9151 80286 Page Interleave Memory Controller (16-25MHz) ?...
**SL9250 80386SX Page Mode Memory Controller (16/20MHz 8MB) ?
***Info:...
***Versions:...
***Features:...
**SL9251 80386SX Page Interleave Memory Controller <04/13/90...
**SL9252 80386SX System and Memory Controller <06/12/90...
**SL9350 80386DX Page Mode Memory Controller (16-25MHz 16MB) ?
***Info:...
***Versions:...
***Features:...
**SL9351 80386DX Page Interleave Memory Controller (33MHz) ?
***Info:...
***Versions:...
***Features:...
**SL9352 80386DX System and Memory Controller <06/12/90...
**SLXXXX Other chips...
**
**VT82C470 "Jupiter", Chip Set (w/o cache) 386 [no datasheet] ?
**VT82C475 "Jupiter", Chip Set (w/cache) 386 [no datasheet] ?
**VT82C486/2/3 "GMC chipset" [no datasheet, some info] ?
***Notes:...
***Info:
8) The VIA GMC chipset (VIA: 1106/4358) (5/18/96)
--------------------
This chipset includes the VIA VT82C486A-F with a built-in 8042
keyboard controller and a VIA VT82C505-D chipset for the VESA to PCI
bridge. Specifically, the chips are as follows:
82C486A - cache/memory controller + VLB to ISA bridge
82C482 - VLB to ISA bridge (why there are two I'm not sure)
82C483 - DRAM controller
VT82C505 PCI to VLB bridge
A board using this chipset has been unstable (even under DOS/Win), and
did not work with an Adaptec 2940 SCSI controller under OS/2 at all.
Boards based on this chipset are therefore to be avoided. I have,
however, had one report of success from someone using revision G of
this chipset, so it could be that the new revision fixes problems with
older rev's. Designers with whom I've corresponded indicate that
improperly designed boards which use this chipset may have unstable
caches. In addition, the cache controller reads the data into the
cache SRAMs first, then into the CPU, increasing latency and reducing
throughput.
***Configurations:...
**VT82C495/480 "Venus" Chip Set [no datasheet] ?
**VT82C495/491 ? EISA Chip Set [no datasheet, some info] <93...
**VT82C496G Pluto, Green PC 80486 PCI/VL/ISA System <05/30/94...
**VT82C530MV 3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M Apollo Master, Green Pentium/P54C <06/22/95...
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97
***Info:...
***Configurations:...
***Features:...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96
***Notes:...
***Info:...
***Configurations:...
***Features:...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI
**Notes:...
**VL82C*** IBM/INTEL Direct replacement ?...
**VL82CPCAT-QC AT 12 MHz 0/1 ws c88...
***Basics:
Max 12MHz "Popular 12 MHz Chip Set"
***Info:
****Overview:...
****VL82C100 ------- PC/AT-Compatible Peripheral Controller...
****VL82C101A/101B - PC/AT-Compatible System Controller...
****VL82C102A ------ PC/AT-Compatible Memory Controller...
****VL82C103/103A -- PC/AT-Compatible Address Buffer...
****VL82C104 - PC/AT-Compatible Data Buffer...
***Configurations:...
***Features:...
**VL82CPCPM-QC AT 16 MHz 0/1 ws [no datasheet] c88...
***Notes:...
**VL82CPCAT-16QC/-20QC AT 16 MHz or 20 MHz, 0/1 ws +386SX c89...
***Basics:...
***Info:...
***Configurations:...
***Features:...
**VL82CPCPM-16QC/-20QC AT 16 MHz or 20 MHz, Page-Mode +386SX c89...
***Basics:...
***Info:...
***Configurations:...
***Features:...
**VL82C031/032/033 PS/2 Model 30-compatible chip set c88...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**VL82C286-SET TOPCAT 286/386SX PC/AT-Compatible Chip Set ?...
***Info:...
***Configurations:...
***Features:...
**VL82C386-SET TOPCAT 386DX PC/AT-Compatible Chip Set ?...
***Info:...
***Configuration:...
***Features:...
**VL82C386sx-SET TOPCAT 286/386SX PC/AT-Compatible Chip Set ?...
***Notes:...
**VL82C310 SCAMP-LT ?...
***Info:...
***Configurations:...
**VL82C311 SCAMP-DT ?...
***Info:...
***Configurations:...
***Features:...
**VL82C311L SCAMP-DT 286 ?...
***Info:...
***Configurations:...
**VL82C312 SCAMP Power Management Unit (PMU) ?...
***Info;...
***Versions:...
***Features:...
**VL82C315A SCAMP II, Low-Power Notebook Chipset ?...
***Info:...
***Configurations:
VL82C315A-FC
Configurations:
VL82C315A
VL82C315A + VL82C325 (Cache controller)
VL82C315A + VL82C322A (PMU)
VL82C315A + VL82C325 + VL82C322A
Either the VL82C113 or the VL82C114 Combination I/O *should* work with
this chip set.
***Features:...
**VL82C322A SCAMP II, Power Management Unit (PMU) ?...
**VL82C316 SCAMP II, PC/AT-Compatible System Controller ?...
**VL82C323 SCAMP II, 5 Volt Power Management Unit (PMU) ?...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?...
**VL82C325 VL82C386SX System Cache controller ?
***Info:...
***Versions:...
***Features:...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
***Notes:...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
***Info:...
***Configurations:...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
***Notes:
from:http://www.cbronline.com/news/vlsi_technology_has_80486sl_notebook_chip_set
The SCAMP IV set comprises three devices - VL82C420 system controller,
VL82C144 peripheral combination chip, and optional VL82C146 ExCA
controller. A standard SCAMP IV system design can be completed with as
few as three TTL components. The devices in the set interconnect via
the VLSI proprietary Multiplexed Local Bus interface; they are
implemented in 0.8 micron CMOS and support mixed voltage operation at
3V and 5V. The VL82C420 is designed to be tightly coupled with the
power-managed Intel CPUs running at up to 33MHz including ones with
clock- doublers. The memory controller supports up to 32Mb.The
peripherals chip also includes floppy disk controller with digital
data separator, a 16C550-compatible universal asynchronous
transmitter-receiver with infra-red support. Power management features
include socket power control, 3.3V/5V suspend with modem and ring
resume detection and power saving with Window inactivity. Up to four
VL82C146s can be used in each system. Samples August, volume October
at $32.50 for the VL82C420, $25.00 for the VL82C144 and $8.50 for the
VL82C146 for 1,000-up.
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?
***Info:...
***Versions:...
***Features:
o High-performance 386DX, 486SX or 486DX interface
o Write buffer - 64 byte (16 DWord)
o External second-level cache - 128 KB
o i486 internal cache control
o BIOS control of second-level cache
o 386SX local bus emulation
o 386SX local bus address pipelining with four word FIFO
o 32-16 bit cycle type translation
o Auto peek cycle operations for both first and second-level cache
o i486 BIOS initialize
o 40 MHz max CPU freq @ 5.0V
33 MHZ max SX freq @ 5.0V
25 MHz max CPU and SX freq @ 3.3V
o Power management plus support for AMD's system Management Mode
(SMM)
o 0.8-micron CMOS technology
o 160-lead metric quad flat pack (MQFP)
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
**Notes:...
**FE2010/A XT CPU controller integrated Circuit >11/22/85...
**FE2011 CPU Core Logic for PS/2 Model 30 Compatible c:87...
**FE3400/B 80286-Based AT Compatible CPU Core Logic (12 MHz) c:86...
**FE3500/B 80286-Based AT Compatible CPU Core Logic (12 MHz) c:87...
**FE3600/A/B/C 16/20MHz AT Chip set c:88...
**FE5300 CPU Core Logic for PS/2 Model 50/60 Compatibles c:87...
**FE5400 CPU Core Logic for PS/2 Model 50/60 Compatibles c:87...
**FE6500 CPU Core Logic for PS/2 Model 70/80 Compatibles c:88
***Notes:...
***Info:
****General:...
****FE6000 Enhanced CPU and Peripheral and Control Logic:...
****FE6010 DMA and Channel Control logic:...
****FE6022 Address and Data Buffer Devices:...
****FE6030 Cache/DRAM and Channel Control Device:...
***Configurations:...
***Features:...
**WD6400SX/LP CPU Core Logic for PS/2 386SX Compatibles <90...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**WD6500 CPU Core Logic for PS/2 386DX/486 Compatible <90...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**WD7600A/LP/LV System Chip Set for 80286 or 80386SX <11/25/91...
***Info:...
***Configurations:...
***Features:...
**WD7700/LP System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
***Info:...
***Configurations:...
***Features:...
**WD7855 System controller for 80386SX <09/25/92...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**WD7900/LP/LV System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**WD8110 System controller for 80386DX/486 <11/30/93...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**
**Support Chips:
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91...
***Info:
GENERAL DESCRIPTION
The WD76C20 is a member of the WD7600 chip set which provides a
cost-effective, power-efficient solution to PC systems design,
especially those relating to "lap-top" devices. The set includes the
WD76C10, the WD76C20, and the WD76C30 as shown in Figure 1-1. Together
these chips provide all necessary logic to build a fully integrated
system board for several varieties of IBM PC/AT compatibles including
systems using 80286, 80386SX, and 80C286 processors.
As part of this chip set, the WD76C20 provides these integral
functions:
o Bus Interface Logic
o IDE Interface
o Chip Select Logic
o Floppy Disk Controller
o Real Time Clock
o Suspend/Resume Logic
The Floppy Disk Controller (FDC) component provides necessary timing
and signalling between the host processor peripheral bus and a floppy
disk drive through a cable connector.
The Real Time Clock component provides calendar and clock information
for the system.
The IDE Interface controls buffering between the system's AT Bus and
PC/AT compatible IDE drive interface.
The Bus Interface Logic controls buffering of data between the
system's AT Bus and the WD76C20.
The Chip Select Logic section provides decoding for selected chip
functions both within the WD76C20 and on the PC/AT motherboard.
Suspend/Resume Logic provides support for chip set power-down and
resume sequences.
***Versions:...
***Features:...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
**Chipsets:
**W83C491/92 VL-Bus chipset (Symphony Wagner SL82C491/2)[no datasheet]
**W83C553F System I/O Controller With PCI Arbiter c:sep95...
**W83628F/29D PCI TO ISA Bridge Set c98...
**W83626F/D LPC TO ISA Bridge Set <00...
**
**Multi I/O:
**W83757 SUPER I/O CHIP <92...
**W83767F ?? Multi I/O [no datasheet]
**W83777F/87F Power I/O (Multi I/O) <95...
**W83877F WINBOND I/O (Multi I/O) <96...
**W83877TF/TG/TD WINBOND I/O (Multi I/O) c97...
**W83977F/G/AF/AG WINBOND I/O (Multi I/O) c97...
**W83977TF WINBOND I/O (Multi I/O) c97...
**W83977EF WINBOND I/O (Multi I/O) <98
***Info:...
***Versions:...
***Features:...
**W83977ATF WINBOND I/O (Multi I/O) <98...
**
**Disk Controller:
**W83759/A/F/AF Advanced VL-IDE Disk Controller <96
***Notes:
Information taken from W83759A datasheet which lists differences to
the W83759. The datasheet is not for the W83759 and W83759A
***Info:...
***Versions:...
***Features:...
**W83769 Local Bus IDE Solution <94
***Info:...
***Versions:...
***Features:...
**
**UARTS:
**W86C250A UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter <Jul89...
**W86C451 I/O controller for IBM PC/AT/XT <Jul89...
**W86C452 I/O controller for IBM PC/AT Jul89...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94...
**
**Other:...
*ZyMOS...
**ZyMOS POACH ...
**Other:...
*General Sources:...
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