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*_IBM...
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*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93
***Info:...
***Versions:...
***Features:...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
**Other:...
**Disk:...
**Video:
F64300 	Wingine DGX 2MB, (appears to be a VLB version adapted from the proprietary 64200)
F64310 	Wingine DGX 2MB  (appears to be a PCI version adapted from the proprietary 64200)

OC65540   VGA BIOS  c:95
OC65545   VGA BIOS same as 540 but has hardware overlay feature.

94C2001   PUMA (Programmable Universal Micro Accelerator) 50MHz Video accelerator

82C840 	  8514/A clone
82C9001A  Video controller

82C404          Programmable clock synthesizer
82C402 	  	VGA clock Synthesizer
82C411          Flat panel color pallet/DAC

82C425 	  	82C425 	CGA, CRT+LCD support, greyscale on LCD, supports two softfonts (up to 8x16 pixels) allowing 512 characters on screen, no snow
82C426 	  	82C426 	CGA, CRT, color LCD+AT&T400 support, max 32KB RAM
82C450 	  	82C450 	1MB VRAM, max 800x600 256color
82C451 	  	82C451 	VGA 256KB DRAM, max 800x600 16color c:90
82C452 	  	82C452 	1MB DRAM, max 640x480 256color, 1024x768 16color
82C453 	  	82C453 	1MB DRAM, max 800x600 256color
82C455 	  	82C455 	256KB DRAM Flat Panel version
82C456, 456A  	82C456 	256KB DRAM Flat Panel/CRT
82C457 	  	82C457 	Full color

82C45x series are VGA

'The 655xx series chips are SVGA video controller chips for flat panel
displays and CRTs. They also provide  some level of CGA, MDA, EGA, and
Hercules  compatibility, and  various accelerator  features. They  are
designed  with various  features  for reducing  power consumption  and
optimizing display quality. 
source:http://www.igl.ku.dk/~fsp/varia/ct5xx.html

see the above source for more details.

82C481 True-Color Graphics Accelerator Wingine?

F65510 	65510 	LCD / CRT
F65520 	65520 	1MB D/VRAM, Full color, max 1280x1024 16color & 800x600 256 color
F65525 	65525 	LCD / CRT
F65530 	65530 	1MB D/VRAM, Full color, max 1280x1024 16color & 800x600 256 color, VLB
F65535 	65535 	LCD / CRT
F65540 	65540 	same as 65545 but without BitBLT and hw cursor
F65545 	65545 	mobile, 512-1024KB DRAM, ISA / PCI / VLB
65546 	  	65546 	 
F65548 	65548 	 
F65550 	65550 	HighQV32, mobile, 1-2MB DRAM, PCI / VLB
B65554 	65554 	HighQV64, mobile, 1-4MB DRAM, BGA
F65555 	65555 	HighQVPro, mobile, 1-4MB EDO, BGA
F68554 	68554 	HiQVision
F68555 	68555 	 
F69000  69000 	
M69000 	69000 	HighQVideo, mobile, 83MHz RAM, 2MB SDRAM on die, PCI / AGPx1, 135MHz RAMDAC, BGA, MiniBGA
F69030 	69030 	HighQVideo, mobile, 100MHz RAM, 4MB SDRAM on die, PCI / AGPx1, 170MHz RAMDAC, BGA, MiniBGA


*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**85C501/502/503 Pentium/P54C PCI/ISA Chipset                <01/09/95
***Notes:...
***Info:...
***Configurations:...
***Features:...
**5101/5102/5103 Pentium/P54C PCI/ISA Chipset                <04/02/95...
**5120           Pentium PCI/ISA Chipset (Mobile)            <01/28/97...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset                <04/02/95...
**5511/5512/5513 Pentium PCI/ISA                             <06/14/95...
**5571           (Trinity) Pentium PCI/ISA Chipset (75MHz)   <12/09/96...
**5581/5582      (Jessie)  Pentium PCI/ISA Chipset (75MHz)   <04/15/97...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
**SL82C470   'Mozart' 486/386 EISA chipset                     c:Dec91
***Info:
The SL82C470 chip set provides  a very high performance.  highly inte-
grated and cost-effective implementation for personal computer systems
based on the  standard EISA bus.  It supports  both 386DX and 486DX/SX
CPUs over the entire performance range, from 20Mhz to 50Mhz.  The chip
set  can  operate in  either  "conventional"  or "concurrent"  config-
uration.  Under the conventional configuration, the cache subsystem is
dedicated to bus snooping when  a DMA or master device becomes active.
Under the concurrent  configuration, the CPU-cache operation continues
while  bus snooping  is  performed for  the  DMA or  master device  to
explore maximum  concurrency between the  CPU and the EISA  bus.  Only
ten  TTLs are  required for  a complete  motherboard design  under the
conventional  configuration in  addition to  the chip  set  and memory
devices.  Five  additional  TTLs   are  required  for  the  concurrent
configuration.  A complete EISA  system of either configuration can be
easily implemented on a baby AT sized motherboard.

The  SL82C470 chip  set consists  of three  160-pin PQFP  devices: the
SL82C471  integrated  cache/DRAM  controller,  the SL82C472  EISA  bus
controller and the SL82C473 DMA controller.

SL820471 Cache/DRAM Controller

The  SL82C47l  Cache/DRAM  controller  controls  the  cache  and  DRAM
accesses from  the CPU,  EISA/ISA masters and  DMA devices.   The chip
adapts a write-back cache  scheme to minimize the interference between
the CPU-cache and DMA/master  during their concurrent operations.  The
cache  size ranges from  64KB to  1MB with  advanced features  such as
2-1-1-1  burst  line fill.   Snoop-filtering,  local  bus support  and
programmable non-cacheable and  write-protected regions. The page mode
DRAM controller supports 1 to 4 banks of DRAMS up to 256MB.  A mixture
of 256KB, 1MB.  4MB and 16MB DRAMs is supported.  The video and system
BIOS  can  be  shadowed   or  cached  independently.   The  cache-DRAM
subsystem allows zero wait state burst mode DMA transfers to take full
advantage of the high bandwidth of the EISA bus.

The DRAM  data bus can either  be connected directly to  the CPU local
bus or  be buffered externally,  The control signals for  the external
buffers are generated by the SL82C471.

SL82C472 EISA Bus Controller

The  SL82C472  EISA  bus  controller translates  bus  control  signals
between the  CPU, EISA/ISA and DMA  masters and slaves.  The chip also
includes buffers  and byte/word swap  logic between the CPU  (or DRAM)
and the EISA bus. The  bus conversion and data alignment are performed
automatically.

The  SL82C472 includes two  8259 interrupt  controllers and  four 8254
timer channels  modified for 100%  EISA compatibility.  The  chip also
includes parity generation and check logic and NMI and timeout logic.

SL82C473 EISA DMA Controller

The SL82C473  DMA controller implements  seven EISA DMA  channels. the
system arbiter and the co-processor interface logic.  The DMA control-
ler  supports compatible  type  A,  type B  and  type  C (burst)  mode
operations  with  the  buffer  chaining  capability.   The  multilevel
rotating priority  arbitration with  fail-safe timeout  is implemented
for the  system arbiter.  Six  sets of slot-specific  master handshake
signals (MACK  and MREQ)  are provided  directly without  any external
components.

The address latches and buffers for  the EISA bus are also included in
the SL82C473.

***Configurations:...
***Features:...
**SL82C490   'Wagner' 486?              [no datasheet]               ?...
**SL82C550   'Rossini' Pentium          [no datasheet]            c:95...
**
**Support Chips:
**SL82C365    Cache Controller (for 386DX/SX)                     c:91...
**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

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